diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-07-20 08:56:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 13:20:40 +0000 |
| commit | 6e0de5d9cc8ba6aefc5407f91a6c00781d19ab8e (patch) | |
| tree | a3e07df368e41dbfb51f04e8da11354d14ae0751 /src/mainboard/ibm/sbp1/devicetree.cb | |
| parent | ef4f2cd38e5ec4d6282e6e9fa97bad7ec8877743 (diff) | |
mb/ibm/sbp1: Drop SuperIO code
The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.
Add the virtual UART on 0x3f8 as ACPI device.
TEST: Verified on SBP1 that serial still works.
Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/ibm/sbp1/devicetree.cb')
| -rw-r--r-- | src/mainboard/ibm/sbp1/devicetree.cb | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb index 99c14b17f5..6fee7b88b0 100644 --- a/src/mainboard/ibm/sbp1/devicetree.cb +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -6,15 +6,6 @@ chip soc/intel/xeon_sp/spr device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 device pci 1f.0 on # Intel device 1b81: PCH eSPI controller - chip superio/common - device pnp 2e.0 on - chip superio/aspeed/ast2400 - register "use_espi" = "1" - device pnp 2e.2 off end # SUART1 - device pnp 2e.3 off end # SUART2 - end - end - end chip drivers/ipmi # BMC KCS device pnp ca2.0 on end register "bmc_i2c_address" = "0x20" |