diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-07-20 08:56:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 13:20:40 +0000 |
| commit | 6e0de5d9cc8ba6aefc5407f91a6c00781d19ab8e (patch) | |
| tree | a3e07df368e41dbfb51f04e8da11354d14ae0751 /src/mainboard/ibm/sbp1/bootblock.c | |
| parent | ef4f2cd38e5ec4d6282e6e9fa97bad7ec8877743 (diff) | |
mb/ibm/sbp1: Drop SuperIO code
The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.
Add the virtual UART on 0x3f8 as ACPI device.
TEST: Verified on SBP1 that serial still works.
Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/ibm/sbp1/bootblock.c')
| -rw-r--r-- | src/mainboard/ibm/sbp1/bootblock.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c index e04d8ef6be..bb18228548 100644 --- a/src/mainboard/ibm/sbp1/bootblock.c +++ b/src/mainboard/ibm/sbp1/bootblock.c @@ -8,24 +8,21 @@ #include <soc/intel/common/block/lpc/lpc_def.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <superio/aspeed/ast2400/ast2400.h> -#include <superio/aspeed/common/aspeed.h> -#define ASPEED_SIO_PORT 0x2E #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 void bootblock_mainboard_early_init(void) { uint16_t lpciod = LPC_IOD_COMA_RANGE; - uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN); + uint16_t lpcioe = LPC_IOE_COMA_EN; /* Open IO windows: 0x3f8 for com1 */ pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); /* LPC I/O enable: com1 */ pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); - /* Enable com1 (0x3f8) and superio (0x2e) */ + /* Enable com1 (0x3f8) */ pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); } |