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authorNaresh Solanki <Naresh.Solanki@9elements.com>2023-05-24 10:29:45 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2023-05-28 20:11:25 +0000
commitc7338085feaba70d9f67d2dd797624cddae84e7c (patch)
tree288f10b2352e7096b09ef3fd023610f8cdece9e9 /src/mainboard/ibm/sbp1/board.fmd
parent6230d4131881e9fa51d1099652605c890f93f53d (diff)
soc/intel/xeon_sp: Enable build for IO Margining
This commit enables the build for IO Margining, ensuring that ASPM is disabled and certain FSP knobs are adjusted in coreboot as below 1. Enable DFXEnable 2. Disable PcieGlobalAspm 3. Disable KtiLinkL1En & KtiLinkL0pEn Since the FSP UPD does not provide all the necessary knobs for IO Margining, the following settings need to be applied during the FSP build process: 1. Enable PcdBiosDfxKnobEnabled 2. Disable PchDmiAspm 3. Enable SataTestMode 4. Enable WmphyMargining 5. Disable IioErrorEn TEST=Build for IBM sbp1 board. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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