diff options
author | Li-Ta Lo <ollie@lanl.gov> | 2004-04-28 18:49:24 +0000 |
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committer | Li-Ta Lo <ollie@lanl.gov> | 2004-04-28 18:49:24 +0000 |
commit | fcdd571aee7592bd3f67283e70fba7608091ba04 (patch) | |
tree | c5171b1b3dd20ac7858182b0cc7bf9c602f63bb7 /src/mainboard/ibm/e325/mptable.c | |
parent | 500497fc34189473f989add8f281bcbf90c341c9 (diff) |
corrected irq and mp table according to new bus enumeration
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ibm/e325/mptable.c')
-rw-r--r-- | src/mainboard/ibm/e325/mptable.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 68c30fcaeb..bc9d52f262 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -41,34 +41,34 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) device_t dev; /* 8111 */ - dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } else { - printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n"); + printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(0, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n"); + printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n"); + printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); bus_8131_2 = 3; } } @@ -85,14 +85,14 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) device_t dev; uint32_t base; /* 8131-1 apic #3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x01,1)); + dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); if (dev) { base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base &= PCI_BASE_ADDRESS_MEM_MASK; smp_write_ioapic(mc, 0x03, 0x11, base); } /* 8131-2 apic #4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x02,1)); + dev = dev_find_slot(1, PCI_DEVFN(0x02,1)); if (dev) { base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base &= PCI_BASE_ADDRESS_MEM_MASK; |