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author | Subrata Banik <subrata.banik@intel.com> | 2020-10-10 15:53:33 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-14 14:49:01 +0000 |
commit | 9b4f221026d16cc4b6dc0eadad074ef44ff1ffed (patch) | |
tree | 2364bf72a16bb278d66b0a8b718fe03edf7a912b /src/mainboard/hp | |
parent | 522ba1ba27bcfef8166fc1345160a32e250c01ca (diff) |
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes:
1. Add devicetree.cb config parameters related to FSP-S UPD
2. Configure GPIO as per ADL-P RVP
3. Add files required for ramstage(ec.c, mainboard.c)
4. Add smihandler.c for SMM
5. Add devicetree changes as below
- USB OC PIN programing
- GPE configuration
- SATA port mapping
- LPSS configuration
- Audio configuration
- IA common SoC configuration
- EDP configuration
- TCSS USB configuration
- Enable S0ix
TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with
UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till
depthcharge payload.
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/hp')
0 files changed, 0 insertions, 0 deletions