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author | Stefan Reinauer <reinauer@chromium.org> | 2011-10-31 12:56:45 -0700 |
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committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-01 19:07:45 +0100 |
commit | 5ff7c13e858a31addf1558731a12cf6c753b576d (patch) | |
tree | 82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src/mainboard/hp | |
parent | 784544b934d67dc85ccfcf33e04ff148045836ad (diff) |
remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/hp')
-rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d40df6b95d..32a94d425b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0, val; msr_t msr; - + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ |