diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-20 23:19:17 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-05-26 11:31:57 +0000 |
| commit | 927f6ae84a7b59b630250a7e559aac1eb05ae2f5 (patch) | |
| tree | a88e11d08b70b07e91504281cfb9fe633e604ad5 /src/mainboard/hp | |
| parent | 477b4f8886bd5bca8a6c26035e0ab20a8709298a (diff) | |
mb/*/*/buildOpts.c: Drop BLDCFG_IR_PIN_CONTROL
This does not exist anywhere in the entire coreboot tree. Drop it.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/mainboard/hp')
| -rw-r--r-- | src/mainboard/hp/abm/buildOpts.c | 1 | ||||
| -rw-r--r-- | src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 337d35cf7a..05ed0147aa 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -310,7 +310,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL hp_abm_gpio[] = { { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 989df12da0..c46ba74f82 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 /* * The GPIO control is not well documented in AGESA, but is in the BKDG |