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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-26 22:42:41 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-26 22:42:41 +0000 |
| commit | 39124dd6c5f577861c16b947088ac1fd31169b8f (patch) | |
| tree | b2b82e8557f45fddb5fa654703e2bd6876ff4b2f /src/mainboard/hp | |
| parent | e89d8a57accbac5066f80266d1e98e63f62ba4c5 (diff) | |
Broadcom BCM5785: Add TINY_BOOTBLOCK support.
In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
and use 'dev' instead of 'addr' as device_t variable name.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/hp')
| -rw-r--r-- | src/mainboard/hp/dl145_g3/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index ff16b3f8bb..eeac3e5b6a 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -41,7 +41,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -145,7 +144,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - bcm5785_enable_rom(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index f167b925ac..ae9be8aeea 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -40,7 +40,6 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> @@ -109,7 +108,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - bcm5785_enable_rom(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } |