diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:04:22 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:41:11 +0000 |
| commit | 1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch) | |
| tree | bf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/hp | |
| parent | f054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff) | |
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/hp')
29 files changed, 0 insertions, 3524 deletions
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig deleted file mode 100644 index 74ce0e726c..0000000000 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -if BOARD_HP_DL145_G1 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_940 - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_AMD_AMD8131 - select SOUTHBRIDGE_AMD_AMD8111 - select HT_CHAIN_DISTRIBUTE - select SUPERIO_WINBOND_W83627HF - select HAVE_HARD_RESET - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_512 - select SET_FIDVID - select SET_FIDVID_DEBUG - select RAMINIT_SYSINFO -# select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select QRANK_DIMM_SUPPORT - select DRIVERS_I2C_I2CMUX - select HAVE_ACPI_TABLES - -config MAINBOARD_DIR - string - default hp/dl145_g1 - -config APIC_ID_OFFSET - hex - default 0x0 - -config MAINBOARD_PART_NUMBER - string - default "ProLiant DL145 G1" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x6 - -config IRQ_SLOT_COUNT - int - default 9 - -endif # BOARD_HP_DL145_G1 diff --git a/src/mainboard/hp/dl145_g1/Kconfig.name b/src/mainboard/hp/dl145_g1/Kconfig.name deleted file mode 100644 index 2840287608..0000000000 --- a/src/mainboard/hp/dl145_g1/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_DL145_G1 - bool "ProLiant DL145 G1" diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl deleted file mode 100644 index 8de268bd15..0000000000 --- a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl +++ /dev/null @@ -1,617 +0,0 @@ -/* - * Copyright 2005 AMD - * Copyright (C) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se> - */ -//AMD8111 -// APIC version of the interrupt routing table -Name (APIC, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} -}) -// PIC version of the interrupt routing table -Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} -}) -Name (DNCG, Ones) -Method (_PRT, 0, NotSerialized) { - If (LEqual (^DNCG, Ones)) { - Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) - // Update the Device Number according to SBDN - Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) - - Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - - Store (0x00, ^DNCG) - } - - If (LNot (PICF)) { - Return (PICM) - } Else { - Return (APIC) - } -} - -// AMD8111 System Management I/O Mapped Registers (PMxx) -OperationRegion (PMIO, SystemIO, PMBS, 0xDF) -Field (PMIO, ByteAcc, NoLock, Preserve) { - Offset (0x1E), - SWSM, 8, // Software SMI Trigger (sets GSTS) - Offset (0x28), - GSTS, 16, // Global STatuS - GNBL, 16, // Global SMI enable - Offset (0x30), - STMC, 5, // Miscellaneous SMI Status - Offset (0x32), - ENMC, 5, // Miscellaneous SMI Enable - Offset (0x44), - STC0, 9, // TCO Status 1 - Offset (0x46), - STC1, 4, // TCO Status 2 - Offset (0xA8), - STHW, 20 // Device monitor SMI Interrupt Enable -} -Device (HPET) { - Name (HPT, 0x00) - Name (_HID, EisaId ("PNP0103")) - Name (_UID, 0x00) - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - Method (_CRS, 0, Serialized) { - Name (BUF0, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) - }) - Return (BUF0) - } -} -#include "amd8111_pic.asl" -#include "amd8111_isa.asl" - -Device (TP2P) { - // 8111 P2P and it should 0x00030000 when 8131 present - Method (_ADR, 0, NotSerialized) { - Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) - } - Method (_PRW, 0, NotSerialized) { // Power Resource for Wake - // result : - // [0] Bit index into GPEx_EN in the GPE block described by FADT. - // [1] The lowest power state from which the system can be awakened. - //If (CondRefOf (\_S3)) { - // Return (Package (0x02) { 0x08, 0x03 }) - //} Else { - Return (Package (0x02) { 0x08, 0x01 }) - //} - } - Device (ETHR) { - Name (_ADR, 0x00010000) - Method (_PRW, 0, NotSerialized) { // Power Resource for Wake - //If (CondRefOf (\_S3)) { - // Return (Package (0x02) { 0x08, 0x03 }) - //} Else { - Return (Package (0x02) { 0x08, 0x01 }) - //} - } - } - Device (USB0) { - Name (_ADR, 0x00000000) - Method (_PSW, 1, NotSerialized) { // Power State Wake - And (GNBL, 0x7FFF, GNBL) - } - Method (_PRW, 0, NotSerialized) { // Power Resource for Wake - //If (CondRefOf (\_S3)) { - // Return (Package (0x02) { 0x0F, 0x03 }) - //} Else { - Return (Package (0x02) { 0x0F, 0x01 }) - //} - } - } - Device (USB1) { - Name (_ADR, 0x00000001) - Method (_PSW, 1, NotSerialized) { // Power State Wake - And (GNBL, 0x7FFF, GNBL) - } - Method (_PRW, 0, NotSerialized) { // Power Resource for Wake - //If (CondRefOf (\_S3)) { - // Return (Package (0x02) { 0x0F, 0x03 }) - //} Else { - Return (Package (0x02) { 0x0F, 0x01 }) - //} - } - } - Name (APIC, Package (0x0C) { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6 - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5 - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } - }) - Name (PICM, Package (0x0C) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6 - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5 - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } - }) - Method (_PRT, 0, NotSerialized) { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } -} -Device (IDE0) { - Method (_ADR, 0, NotSerialized) { - Return (DADD(\_SB.PCI0.SBDN, 0x00010001)) - } - Name (REGF, 0x01) - Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x02)) { - Store (Arg1, REGF) - } - } - OperationRegion (BAR0, PCI_Config, 0x00, 0x60) - Field (BAR0, ByteAcc, NoLock, Preserve) { - Offset (0x40), // EIDE Controller Configuration Register - SCEN, 1, // Secondary Channel Enable - PCEN, 1, // Primary Channel Enable - , 10, - SPWB, 1, // Secondary Port posted-write buffer for PIO modes enable - SRPB, 1, // RW (controls nothing) - PPWB, 1, // Primary Port posted-write buffer for PIO modes enable - PRPB, 1, // RW (controls nothing) - PM80, 1, // High-speed 80-pin cable enable Primary Master - PS80, 1, // High-speed 80-pin cable enable Primary Slave - SM80, 1, // High-speed 80-pin cable enable Secondary Master - SS80, 1, // High-speed 80-pin cable enable Secondary Slave - , 4, // RW (controls nothing) - Offset (0x48), - SSRT, 4, // - SSPW, 4, // - SMRT, 4, // - SMPW, 4, - PSRT, 4, - PSPW, 4, - PMRT, 4, - PMPW, 4, - SSAD, 2, - SMAD, 2, - PSAD, 2, - PMAD, 2, - Offset (0x4E), - SXRT, 4, - SXPW, 4, - PXRT, 4, - PXPW, 4, - SSUD, 8, - SMUD, 8, - PSUD, 8, - PMUD, 8, - PPDN, 1, - PPDS, 1, - , 2, - SPDN, 1, - SPDS, 1 - } - Name (TIM0, Package (0x06) { - Package (0x05) { - 0x78, - 0xB4, - 0xF0, - 0x0186, - 0x0258 - }, - Package (0x07) { - 0x78, - 0x5A, - 0x3C, - 0x2D, - 0x1E, - 0x14, - 0x0F - }, - Package (0x08) { - 0x04, - 0x03, - 0x02, - 0x01, - 0x00, - 0x00, - 0x00, - 0x00 - }, - Package (0x03) { - 0x02, - 0x01, - 0x00 - }, - Package (0x05) { - 0x20, - 0x22, - 0x42, - 0x65, - 0xA8 - }, - Package (0x07) { - 0xC2, - 0xC1, - 0xC0, - 0xC4, - 0xC5, - 0xC6, - 0xC7 - } - }) - Name (TMD0, Buffer (0x14) {}) - CreateDWordField (TMD0, 0x00, PIO0) - CreateDWordField (TMD0, 0x04, DMA0) - CreateDWordField (TMD0, 0x08, PIO1) - CreateDWordField (TMD0, 0x0C, DMA1) - CreateDWordField (TMD0, 0x10, CHNF) - Device (CHN0) { - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) { - If (PCEN) { Return (0x0F) } - Else { Return (0x09) } - } - Method (_GTM, 0, NotSerialized) { - Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD)) - } - Method (_STM, 3, NotSerialized) { - Store (Arg0, TMD0) - Store (STM (), Local0) - And (Local0, 0xFF, PSUD) - ShiftRight (Local0, 0x08, Local0) - And (Local0, 0xFF, PMUD) - ShiftRight (Local0, 0x08, Local0) - And (Local0, 0x0F, PSRT) - ShiftRight (Local0, 0x04, Local0) - And (Local0, 0x0F, PSPW) - ShiftRight (Local0, 0x04, Local0) - And (Local0, 0x0F, PMRT) - ShiftRight (Local0, 0x04, Local0) - And (Local0, 0x0F, PMPW) - Store (GTF (0x00, Arg1), ATA0) - Store (GTF (0x01, Arg2), ATA1) - } - Device (DRV0) { - Name (_ADR, 0x00) - Method (_GTF, 0, NotSerialized) { - Return (RATA (ATA0)) - } - } - Device (DRV1) { - Name (_ADR, 0x01) - Method (_GTF, 0, NotSerialized) { - Return (RATA (ATA1)) - } - } - } - Device (CHN1) { - Name (_ADR, 0x01) - Method (_STA, 0, NotSerialized) { - If (SCEN) { Return (0x0F) } - Else { Return (0x09) } - } - Method (_GTM, 0, NotSerialized) { - Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD)) - } - Method (_STM, 3, NotSerialized) { - Store (Arg0, TMD0) - Store (STM (), Local0) - And (Local0, 0xFF, SSUD) - ShiftRight (Local0, 0x08, Local0) - And (Local0, 0xFF, SMUD) - ShiftRight (Local0, 0x08, Local0) - And (Local0, 0x0F, SSRT) - ShiftRight (Local0, 0x04, Local0) - And (Local0, 0x0F, SSPW) - ShiftRight (Local0, 0x04, Local0) - And (Local0, 0x0F, SMRT) - ShiftRight (Local0, 0x04, Local0) - And (Local0, 0x0F, SMPW) - Store (GTF (0x00, Arg1), ATA2) - Store (GTF (0x01, Arg2), ATA3) - } - Device (DRV0) { - Name (_ADR, 0x00) - Method (_GTF, 0, NotSerialized) { - Return (RATA (ATA2)) - } - } - Device (DRV1) { - Name (_ADR, 0x01) - Method (_GTF, 0, NotSerialized) { - Return (RATA (ATA3)) - } - } - } - Method (GTM, 6, Serialized) { - Store (Ones, PIO0) - Store (Ones, PIO1) - Store (Ones, DMA0) - Store (Ones, DMA1) - Store (0x1A, CHNF) - If (REGF) {} - Else { Return (TMD0) } - Add (Arg0, Arg1, Local0) - Add (Local0, 0x02, Local0) - Multiply (Local0, 0x1E, PIO0) - Add (Arg2, Arg3, Local0) - Add (Local0, 0x02, Local0) - Multiply (Local0, 0x1E, PIO1) - If (And (Arg4, 0x40)) { - Or (CHNF, 0x01, CHNF) - And (Arg4, 0x07, Local0) - If (LLess (Local0, 0x04)) { - Add (Local0, 0x02, Local0) - Multiply (Local0, 0x1E, DMA0) - } Else { - If (LEqual (Local0, 0x04)) { - Store (0x2D, DMA0) - } Else { - If (LEqual (Local0, 0x05)) { - Store (0x1E, DMA0) - } Else { - If (LEqual (Local0, 0x06)) { - Store (0x14, DMA0) - } Else { - If (LEqual (Local0, 0x07)) { - Store (0x0F, DMA0) - } Else { - Store (PIO0, DMA0) - } - } - } - } - } - } Else { - Store (PIO0, DMA0) - } - If (And (Arg5, 0x40)) { - Or (CHNF, 0x04, CHNF) - And (Arg5, 0x07, Local0) - If (LLess (Local0, 0x04)) { - Add (Local0, 0x02, Local0) - Multiply (Local0, 0x1E, DMA1) - } Else { - If (LEqual (Local0, 0x04)) { - Store (0x2D, DMA1) - } Else { - If (LEqual (Local0, 0x05)) { - Store (0x1E, DMA1) - } Else { - If (LEqual (Local0, 0x06)) { - Store (0x14, DMA1) - } Else { - If (LEqual (Local0, 0x07)) { - Store (0x0F, DMA0) - } Else { - Store (PIO1, DMA1) - } - } - } - } - } - } Else { - Store (PIO1, DMA1) - } - Return (TMD0) - } - Method (STM, 0, Serialized) { - If (REGF) {} - Else { Return (0xFFFFFFFF) } - If (LEqual (PIO0, 0xFFFFFFFF)) { - Store (0xA8, Local1) - } Else { - And (Match (DerefOf (Index (TIM0, 0x00)), - MGE, PIO0, MTR, - 0x00, 0x00), - 0x07, Local0) - Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)), - Local1) - } - ShiftLeft (Local1, 0x08, Local1) - If (LEqual (PIO1, 0xFFFFFFFF)) { - Or (Local1, 0xA8, Local1) - } Else { - And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR, - 0x00, 0x00), 0x07, Local0) - Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)), - Local1, Local1) - } - ShiftLeft (Local1, 0x08, Local1) - If (LEqual (DMA0, 0xFFFFFFFF)) { - Or (Local1, 0x03, Local1) - } Else { - If (And (CHNF, 0x01)) { - And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR, - 0x00, 0x00), 0x07, Local0) - Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)), - Local1, Local1) - } Else { - Or (Local1, 0x03, Local1) - } - } - ShiftLeft (Local1, 0x08, Local1) - If (LEqual (DMA1, 0xFFFFFFFF)) { - Or (Local1, 0x03, Local1) - } Else { - If (And (CHNF, 0x04)) { - And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR, - 0x00, 0x00), 0x07, Local0) - Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)), - Local1, Local1) - } Else { - Or (Local1, 0x03, Local1) - } - } - Return (Local1) - } - Name (AT01, Buffer (0x07) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF - }) - Name (AT02, Buffer (0x07) { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90 - }) - Name (AT03, Buffer (0x07) { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6 - }) - Name (AT04, Buffer (0x07) { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91 - }) - Name (ATA0, Buffer (0x1D) {}) - Name (ATA1, Buffer (0x1D) {}) - Name (ATA2, Buffer (0x1D) {}) - Name (ATA3, Buffer (0x1D) {}) - Name (ATAB, Buffer (0x1D) {}) - CreateByteField (ATAB, 0x00, CMDC) - Method (GTFB, 3, Serialized) { - Multiply (CMDC, 0x38, Local0) - Add (Local0, 0x08, Local1) - CreateField (ATAB, Local1, 0x38, CMDX) - Multiply (CMDC, 0x07, Local0) - CreateByteField (ATAB, Add (Local0, 0x02), A001) - CreateByteField (ATAB, Add (Local0, 0x06), A005) - Store (Arg0, CMDX) - Store (Arg1, A001) - Store (Arg2, A005) - Increment (CMDC) - } - Method (GTF, 2, Serialized) { - Store (Arg1, Debug) - Store (0x00, CMDC) - Name (ID49, 0x0C00) - Name (ID59, 0x00) - Name (ID53, 0x04) - Name (ID63, 0x0F00) - Name (ID88, 0x0F00) - Name (IRDY, 0x01) - Name (PIOT, 0x00) - Name (DMAT, 0x00) - If (LEqual (SizeOf (Arg1), 0x0200)) { - CreateWordField (Arg1, 0x62, IW49) - Store (IW49, ID49) - CreateWordField (Arg1, 0x6A, IW53) - Store (IW53, ID53) - CreateWordField (Arg1, 0x7E, IW63) - Store (IW63, ID63) - CreateWordField (Arg1, 0x76, IW59) - Store (IW59, ID59) - CreateWordField (Arg1, 0xB0, IW88) - Store (IW88, ID88) - } - Store (0xA0, Local7) - If (Arg0) { - Store (0xB0, Local7) - And (CHNF, 0x08, IRDY) - If (And (CHNF, 0x10)) { - Store (PIO1, PIOT) - } Else { - Store (PIO0, PIOT) - } - If (And (CHNF, 0x04)) { - If (And (CHNF, 0x10)) { - Store (DMA1, DMAT) - } Else { - Store (DMA0, DMAT) - } - } Else { - Store (PIO1, DMAT) - } - } Else { - And (CHNF, 0x02, IRDY) - Store (PIO0, PIOT) - If (And (CHNF, 0x01)) { - Store (DMA0, DMAT) - } - } - If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) { - Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR, - 0x00, 0x00), Local1) - If (LGreater (Local1, 0x06)) { - Store (0x06, Local1) - } - GTFB (AT01, Or (0x40, Local1), Local7) - } Else { - If (LAnd (And (ID63, 0xFF00), PIOT)) { - And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, - 0x00, 0x00), 0x07, Local0) - If (Local0) { - If (And (Local0, 0x04)) { - Store (0x02, Local0) - } Else { - Store (0x01, Local0) - } - } - Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0 - )), Local1) - GTFB (AT01, Local1, Local7) - } - } - If (IRDY) { - And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, - 0x00, 0x00), 0x07, Local0) - Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0 - )), Local1) - GTFB (AT01, Local1, Local7) - } Else { - If (And (ID49, 0x0400)) { - GTFB (AT01, 0x01, Local7) - } - } - If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) { - GTFB (AT03, And (ID59, 0xFF), Local7) - } - Store (ATAB, Debug) - Return (ATAB) - } - Method (RATA, 1, NotSerialized) { - CreateByteField (Arg0, 0x00, CMDN) - Multiply (CMDN, 0x38, Local0) - CreateField (Arg0, 0x08, Local0, RETB) - Store (RETB, Debug) - Return (RETB) - } -} -Device (PMF) { - // ACPI smbus it should be 0x00040003 if 8131 present - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) - } - OperationRegion (BAR0, PCI_Config, 0x00, 0xff) - Field (BAR0, ByteAcc, NoLock, Preserve) { - Offset (0x56), - PIRA, 4, - PIRB, 4, - PIRC, 4, - PIRD, 4 - } - //OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) - //Field (TS3_, DWordAcc, NoLock, Preserve) { - // PTS3, 16 - //} -} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl deleted file mode 100644 index be2a1ffdb4..0000000000 --- a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright 2005 AMD - * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - */ -//AMD8111 isa - -Device (ISA) { - // lpc 0x00040000 - Method (_ADR, 0, NotSerialized) { - Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) - } - /* - OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers - Field (PIRY, ByteAcc, NoLock, Preserve) { - Z000, 2, // Parallel Port Range - , 1, - ECP , 1, // ECP Enable - FDC1, 1, // Floppy Drive Controller 1 - FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), - Z001, 3, // Serial Port A Range - SAEN, 1, // Serial Post A Enabled - Z002, 3, // Serial Port B Range - SBEN, 1 // Serial Post B Enabled - } - */ - Device (PIC) { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) // Master Interrupt controller - IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) // Slave Interrupt controller - IRQ (Edge, ActiveHigh, Exclusive) {2} - }) - } - Device (DMA1) { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) // Slave DMA controller - IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) // DMA page registers - IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) // Master DMA controller - DMA (Compatibility, NotBusMaster, Transfer16) {4} - }) - } - Device (TMR) { - Name (_HID, EisaId ("PNP0100")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) // Programmable Interval timer - IRQ (Edge, ActiveHigh, Exclusive) {0} - }) - } - Device (RTC) { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0070, 0x0070, 0x01, 0x04) // Realtime Clock and CMOS ram - IRQ (Edge, ActiveHigh, Exclusive) {8} - }) - } - Device (SPKR) { - Name (_HID, EisaId ("PNP0800")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) // PC speaker - }) - } - Device (COPR) { // Co-processor - Name (_HID, EisaId ("PNP0C04")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) // Floating point Error control - IRQ (Edge, ActiveHigh, Exclusive) {13} - }) - } - Device (SYSR) { // System control registers (?) - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x00) - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) - IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C) - IO (Decode16, 0x0080, 0x0080, 0x01, 0x01) - IO (Decode16, 0x0084, 0x0084, 0x01, 0x03) - IO (Decode16, 0x0088, 0x0088, 0x01, 0x01) - IO (Decode16, 0x008C, 0x008C, 0x01, 0x03) - IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - // IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - // EISA defined level triggered interrupt control registers - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) - // IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - // IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80) - // IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80) - IO (Decode16,0xDE00,0xDE00,0x00,0x80) - IO (Decode16,0xDE80,0xDE80,0x00,0x80) - // IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM - // IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) - IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block - IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block - IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block - }) - Method (_CRS, 0, NotSerialized) { - CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00) - CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01) - CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L) - Store (PMBS, GP00) - Store (PMBS, GP01) - Store (PMLN, GP0L) - If (SMBS) { - CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10) - CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11) - CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L) - Store (SMBS, GP10) - Store (SMBS, GP11) - Store (SMBL, GP1L) - } - If (GPBS) { - CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20) - CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21) - CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L) - Store (GPBS, GP20) - Store (GPBS, GP21) - Store (GPLN, GP2L) - } - Return (CRS) - } - } - Device (MEM) { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - Method (_CRS, 0, Serialized) { - Name (BUF0, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF - Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC - Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC - Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - }) -// Read the Video Memory length - CreateDWordField (BUF0, 0x14, CLEN) - CreateDWordField (BUF0, 0x10, CBAS) - - ShiftLeft (VGA1, 0x09, Local0) - Store (Local0, CLEN) - - Return (BUF0) - } - } -#include "superio/winbond/w83627hf/acpi/superio.asl" -} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl deleted file mode 100644 index a09c576102..0000000000 --- a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2005 AMD - * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - */ -//AMD8111 pic LNKA B C D - -Device (LNKA) { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x01) - Method (_STA, 0, NotSerialized) { - If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - Method (_PRS, 0, Serialized) { - Name (BUFA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - Method (_DIS, 0, NotSerialized) { - Store (0x00, \_SB.PCI0.PMF.PIRA ) - } - - Method (_CRS, 0, Serialized) { - Name (BUFA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local2) - Store (0x00, Local3) - Store (\_SB.PCI0.PMF.PIRA, Local1) - If (LNot (LEqual (Local1, 0x00))) { // Routing enable - If (LGreater (Local1, 0x07)) { - Subtract (Local1, 0x08, Local1) - ShiftLeft (One, Local1, Local3) - } Else { - If (LGreater (Local1, 0x00)) { - ShiftLeft (One, Local1, Local2) - } - } - Store (Local2, IRA1) - Store (Local3, IRA2) - } - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - Store(Local1,\_SB.PCI0.PMF.PIRA) - } -} - -Device (LNKB) { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) { - If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - - Method (_PRS, 0, Serialized) { - Name (BUFB, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) { - Store (0x00, \_SB.PCI0.PMF.PIRB ) - } - - Method (_CRS, 0, Serialized) { - Name (BUFB, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRA1) - CreateByteField (BUFB, 0x02, IRA2) - Store (0x00, Local2) - Store (0x00, Local3) - Store (\_SB.PCI0.PMF.PIRB, Local1) - If (LNot (LEqual (Local1, 0x00))) { // Routing enable - If (LGreater (Local1, 0x07)) { - Subtract (Local1, 0x08, Local1) - ShiftLeft (One, Local1, Local3) - } Else { - If (LGreater (Local1, 0x00)) { - ShiftLeft (One, Local1, Local2) - } - } - Store (Local2, IRA1) - Store (Local3, IRA2) - } - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - Store(Local1,\_SB.PCI0.PMF.PIRB) - } -} - -Device (LNKC) { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x03) - Method (_STA, 0, NotSerialized) { - If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - - Method (_PRS, 0, Serialized) { - Name (BUFA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) { - Store (0x00, \_SB.PCI0.PMF.PIRC ) - } - - Method (_CRS, 0, Serialized) { - Name (BUFA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local2) - Store (0x00, Local3) - Store (\_SB.PCI0.PMF.PIRC, Local1) - If (LNot (LEqual (Local1, 0x00))) { // Routing enable - If (LGreater (Local1, 0x07)) { - Subtract (Local1, 0x08, Local1) - ShiftLeft (One, Local1, Local3) - } Else { - If (LGreater (Local1, 0x00)) { - ShiftLeft (One, Local1, Local2) - } - } - Store (Local2, IRA1) - Store (Local3, IRA2) - } - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - Store(Local1,\_SB.PCI0.PMF.PIRC) - } -} - -Device (LNKD) { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x04) - Method (_STA, 0, NotSerialized) { - If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - Method (_PRS, 0, Serialized) { - Name (BUFB, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - Method (_DIS, 0, NotSerialized) { - Store (0x00, \_SB.PCI0.PMF.PIRD ) - } - Method (_CRS, 0, Serialized) { - Name (BUFB, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRA1) - CreateByteField (BUFB, 0x02, IRA2) - Store (0x00, Local2) - Store (0x00, Local3) - Store (\_SB.PCI0.PMF.PIRD, Local1) - If (LNot (LEqual (Local1, 0x00))) { // Routing enable - If (LGreater (Local1, 0x07)) { - Subtract (Local1, 0x08, Local1) - ShiftLeft (One, Local1, Local3) - } Else { - If (LGreater (Local1, 0x00)) { - ShiftLeft (One, Local1, Local2) - } - } - Store (Local2, IRA1) - Store (Local3, IRA2) - } - Return (BUFB) - } - Method (_SRS, 1, NotSerialized) { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - Store(Local1,\_SB.PCI0.PMF.PIRD) - } -} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl deleted file mode 100644 index 29808aabd9..0000000000 --- a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright 2005 AMD - * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - */ - -Device (PG0A) { -/* 8131 pcix bridge 1 */ - Method (_ADR, 0, NotSerialized) { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - Method (_PRW, 0, NotSerialized) { - //If (CondRefOf (\_S3)) { - // Return (Package (0x02) { 0x29, 0x03 }) - //} Else { - Return (Package (0x02) { 0x29, 0x01 }) - //} - } - Name (APIC, Package (0x0c) { - // Slot 3 - PIRQ BCDA ---- verified - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - // Slot 4 - PIRQ CDAB ---- verified - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, - // Onboard NIC 1 - PIRQ DABC - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, - // NIC 2 - PIRQ ABCD -- verified - // Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? - // Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, - // Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, - // Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, - // SERIAL ATA - PIRQ BCDA - // Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? - // Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, - // Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, - // Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } - }) - Name (PICM, Package (0x0c) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - // Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - // Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - // Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - // Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - // Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - // Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - // Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - // Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } - }) - Method (_PRT, 0, NotSerialized) { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } -} -Device (PG0B) { -/* 8131 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - Method (_PRW, 0, NotSerialized) { - //If (CondRefOf (\_S3)) { - // Return (Package (0x02) { 0x22, 0x03 }) - //} Else { - Return (Package (0x02) { 0x22, 0x01 }) - //} - } - Name (APIC, Package (0x04) { - // Slot A - PIRQ CDAB -- verfied - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2 - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C }, - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D }, - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E } - }) - Name (PICM, Package (0x04) { - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2 - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 } - }) - Method (_PRT, 0, NotSerialized) { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } -} diff --git a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl deleted file mode 100644 index 021ee1f279..0000000000 --- a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se> - * Subject to the GNU GPL v2, or (at your option) any later version. - */ -#include "amd8111.asl" //real SB at first -#include "amd8131.asl" diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c deleted file mode 100644 index a464678036..0000000000 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Island Aruma ACPI support - * written by Stefan Reinauer <stepan@openbios.org> - * (C) 2005 Stefan Reinauer - * - * Copyright 2005 AMD - * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB - * - * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * Modified to work with hp/dl145_g1 - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/amd/amdk8_sysconf.h> -#include "northbridge/amd/amdk8/acpi.h" -#include "mb_sysconf.h" -#include <cpu/amd/powernow.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - unsigned int gsi_base = 0x18; - - struct mb_sysconf_t *m; - - get_bus_conf(); - - m = sysconf.mb; - - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write 8111 IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, - IO_APIC_ADDR, 0); - - /* Write all 8131 IOAPICs */ - { - struct device *dev; - struct resource *res; - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_1, - res->base, gsi_base ); - gsi_base+=4; - - } - } - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_2, - res->base, gsi_base ); - gsi_base+=4; - } - } - - - } - - current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) - current, 0, 0, 2, 5 ); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high*/ - - - /* create all subtables for processors */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); - /* 1: LINT1 connect to NMI */ - - - return current; -} diff --git a/src/mainboard/hp/dl145_g1/board_info.txt b/src/mainboard/hp/dl145_g1/board_info.txt deleted file mode 100644 index b06f119a91..0000000000 --- a/src/mainboard/hp/dl145_g1/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: server -Board URL: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c00346784&prodTypeId=15351&prodSeriesId=3219755 -ROM package: PLCC -ROM protocol: LPC -ROM socketed: y -Flashrom support: y -Release year: 2004 diff --git a/src/mainboard/hp/dl145_g1/cmos.layout b/src/mainboard/hp/dl145_g1/cmos.layout deleted file mode 100644 index c4c90f697f..0000000000 --- a/src/mainboard/hp/dl145_g1/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb deleted file mode 100644 index 2d4adee0f4..0000000000 --- a/src/mainboard/hp/dl145_g1/devicetree.cb +++ /dev/null @@ -1,141 +0,0 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x7460 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on # link 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on # PCIX Bridge A - # PCI-X expansion slot cards auto-detected here - end - device pci 0.1 on end # IOAPIC A - device pci 1.0 on # PCIX Bridge B - # On-board BCM5704 dual port ethernet chip auto-detected here - # Optional SCSI board also (?) - end - device pci 1.1 on end # IOAPIC B - device pci 2.0 off end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent of the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end # OHCI-based USB controller 0 - device pci 0.1 on end # OCHI-based USB controller 1 - device pci 0.2 on end # EHCI-based USB2 controller - device pci 1.0 off end # LAN Ethernet controller - #device pci 4.0 on end # VGA PCI-card (auto detected) - end - device pci 1.0 on # LPC Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - #io 0x60 = 0x3f0 - #irq 0x70 = 6 - #drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - #io 0x60 = 0x378 - #irq 0x70 = 7 - #drq 0x74 = 1 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - #io 0x60 = 0x2f8 - #irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - end - device pnp 2e.7 off # GAM_MIDI_GPIO1 - #io 0x60 = 0x201 - #io 0x62 = 0x330 - #irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 (watchdog timer) - end - device pnp 2e.9 on # GPIO3 - end - device pnp 2e.a on # ACPI - end - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end # EIDE controller - device pci 1.2 on - chip drivers/generic/generic - device i2c 8 on end # Some HW-monitor/sensor? - end - end - device pci 1.2 on - chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms. - device i2c 18 on #0 pca9516 (?) - # Some dimms also listen to address 30-33 - # It's some kind of write-protect function - # The 50-53 addresses are the interesting ones. - chip drivers/generic/generic #dimm H0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm H0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm H0-2 - device i2c 52 on end - end - chip drivers/generic/generic #dimm H0-3 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 (?) - chip drivers/generic/generic #dimm H1-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm H1-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm H1-2 - device i2c 52 on end - end - chip drivers/generic/generic #dimm H1-3 - device i2c 53 on end - end - end - end - end - device pci 1.2 on - chip drivers/generic/generic - device i2c 69 on end # Texas Instruments cdc960 clock synthesizer - end - end # SMBus 2.0 controller - device pci 1.3 on # System management registers (ACPI) - end # System management - #device pci 1.4 off end - device pci 1.5 off end # AC97 Audio - device pci 1.6 off end # AC97 Modem - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl deleted file mode 100644 index bf9787dc79..0000000000 --- a/src/mainboard/hp/dl145_g1/dsdt.asl +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> - * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) -{ - // Name (SPIO, 0x2E) // SuperIO (w83627hf) - Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?) - Name (IO1B, 0x0680) // GPIO Base (?) - Name (IO1L, 0x80) - //Name (IO2B, 0x0295) // Hardware monitor - //Name (IO2L, 0x02) - Name (PMBS, 0x2000) // Power Management Base - Name (PMLN, 0xC0) // Power Management Length - Name (GPBS, 0x20C0) - Name (GPLN, 0x20) - Name (SMBS, 0x20E0) - Name (SMBL, 0x20) - -#define NO_W83627HF_FDC // don't expose the floppy disk controller -#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives -#define NO_W83627HF_PPORT // don't expose the parallel port -//#define NO_W83627HF_UARTA // don't expose the first serial port -#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden - // if UARTB is configured as IRDA port by firmware) -#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is - // configured as serial port by firmware) -#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality -//#define NO_W83627HF_KBC // don't expose the keyboard controller -//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the - // keyboard controller -#define NO_W83627HF_GAME // don't expose the game port -#define NO_W83627HF_MIDI // don't expose the MIDI port -// #define NO_W83627HF_HWMON // don't expose the hardware monitor as - // PnP "Motherboard Resource" -// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT - - Scope (\_SB) { // Root of the bus hierarchy - Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1) - - Device(MBRS) { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - External(_CRS) /* Resource Template in SSDT */ - } - - // The following symbols are assumed to be created by coreboot - External (BUSN) - External (PCIO) - External (MMIO) - External (SBLK) - External (CBST) - External (SBDN) - External (TOM1) // Top Of Memory 1 (low 4GB ?) - External (HCLK) // Hypertransport possible CLocK frequencies - External (HCDN) // Hypertransport Controller Device Numbers - - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) - //Name (_UID, 0x00) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - Method (_BBN, 0, NotSerialized) { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - Method (_CRS, 0, Serialized) { - Name (BUF0, ResourceTemplate () { - // PCI Configuration address space address/data - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - DWordMemory (ResourceProducer, PosDecode, - MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - \_SB.OSVR () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - #include "acpi/pci0_hc.asl" - } - Device (PCI1) { - Name (_HID, "PNP0A03") - Name (_ADR, 0x00190000) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) { - Return (\_SB.PCI0.CBST) - } - //Name (HCIN, 0x01) // HC2 - //Method (_BBN, 0, NotSerialized) { - // Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - //} - Name (_BBN, 0x00) - } - Device (PWRB) { - Name (_HID, EisaId ("PNP0C0C")) - Name (_UID, 0xAA) - Name (_STA, 0x0B) - } - } - Scope (_GPE) { - Method (_L08, 0, NotSerialized) { - Notify (\_SB.PCI0, 0x02) //PME# Wakeup - Notify (\_SB.PCI0.TP2P.ETHR, 0x02) - Notify (\_SB.PWRB, 0x02) - } - Method (_L0F, 0, NotSerialized) { - Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - Notify (\_SB.PCI0.TP2P.USB1, 0x02) - Notify (\_SB.PWRB, 0x02) - } - Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B - Notify (\_SB.PCI0.PG0B, 0x02) - Notify (\_SB.PWRB, 0x02) - } - Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A - Notify (\_SB.PCI0.PG0A, 0x02) - Notify (\_SB.PWRB, 0x02) - } - } - OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?) - Field (KSB0, ByteAcc, NoLock, Preserve) { - KSBI, 8, // Index - KSBD, 8 // Data - } -/* - OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor - Field (IHHM, ByteAcc, NoLock, Preserve) { - HHMI, 8, // Index - HHMD, 8 // Data - } -*/ - // Method (_BFS, 1, NotSerialized) { - // Control method executed immediately following a wake event. - // Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...) - // Optional - //} - - Method (_PTS, 1, NotSerialized) { - // Control method used to Prepare To Sleep. - // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG8) - } - - // Method (_GTS, 1, NotSerialized) { - // Control method executed just prior to setting the sleep enable (SLP_EN) bit. - // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) - // Optional - //} - - #include <southbridge/amd/amd8111/acpi/sleepstates.asl> - - Name (WAKP, Package (0x02) { 0x00, 0x00 }) - // Status - // 0: 0 Wake was signaled but failed due to lack of power. - // 1: 1 Wake was signaled but failed due to thermal condition - // 2:31 Reserved - // PSS - // 0:1f If non-zero, the effective S-state the power supply really entered. - - Method (_WAK, 1, NotSerialized) { - // System Wake - // Arg0: The value of the sleeping state from which woken (1=S1, ...) - // Result: (2 DWORD package) - ShiftLeft (Arg0, 0x04, DBG8) - Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM - Store (0x00, KSBD) - If (LEqual (Arg0, 0x01)) { // Wake from S1 state - And (\_SB.PCI0.GSTS, 0x10, Local0) - And (Local0, \_SB.PCI0.GNBL, Local0) - If (Local0) { - Notify (\_SB.PWRB, 0x02) - } - } - Store (\_SB.PCI0.GSTS, Local0) - Store (Local0, \_SB.PCI0.GSTS) - Store (\_SB.PCI0.STMC, Local0) - Store (Local0, \_SB.PCI0.STMC) - Store (\_SB.PCI0.STC0, Local0) - Store (Local0, \_SB.PCI0.STC0) - Store (\_SB.PCI0.STC1, Local0) - Store (Local0, \_SB.PCI0.STC1) - Store (\_SB.PCI0.STHW, Local0) - Store (Local0, \_SB.PCI0.STHW) - If (LEqual (Arg0, 0x03)) { // Wake from S3 state - Notify (\_SB.PCI0.TP2P.USB0, 0x01) - } - Store (0xC0, \_SB.PCI0.SWSM) - If (DerefOf (Index (WAKP, 0x00))) { - Store (0x00, Index (WAKP, 0x01)) - } Else { - Store (Arg0, Index (WAKP, 0x01)) - } - Return (WAKP) - } - - Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode - Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method - // Control method that conveys interrupt model in use to the system - // firmware. OS reports interrupt model in use. - // 0 => PIC Mode - // 1 => APIC Mode - // 2 => SAPIC Mode - // 3.. => Reserved - Store (Arg0, PICF) - } - OperationRegion (DEB8, SystemIO, 0x80, 0x01) - Field (DEB8, ByteAcc, Lock, Preserve) { - DBG8, 8 - } - OperationRegion (DEB9, SystemIO, 0x90, 0x01) - Field (DEB9, ByteAcc, Lock, Preserve) { - DBG9, 8 - } - OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) - Field (EXTM, WordAcc, Lock, Preserve) { - AMEM, 32 - } - OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) - Field (VGAM, ByteAcc, Lock, Preserve) { - VGA1, 8 // Video memory length (in 2k units?) - } - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), - FLG0, 8 - } - OperationRegion (Z007, SystemIO, 0x21, 0x01) - Field (Z007, ByteAcc, NoLock, Preserve) { - Z008, 8 - } - OperationRegion (Z009, SystemIO, 0xA1, 0x01) - Field (Z009, ByteAcc, NoLock, Preserve) { - Z00A, 8 - } - #include "northbridge/amd/amdk8/util.asl" -} diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c deleted file mode 100644 index 877cb5b03b..0000000000 --- a/src/mainboard/hp/dl145_g1/fadt.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org> - * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - */ - -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> - -extern unsigned pm_base; /* pm_base should be set in sb ACPI */ - -void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ - - acpi_header_t *header=&(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt,0,sizeof(acpi_fadt_t)); - memcpy(header->signature,"FACP",4); - header->length = 244; - header->revision = 3; - memcpy(header->oem_id,OEM_ID,6); - memcpy(header->oem_table_id,"COREBOOT",8); - memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl=(u32)facs; - fadt->dsdt= (u32)dsdt; - // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server - fadt->preferred_pm_profile = 0x04; - fadt->sci_int = 9; - - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = pm_base+0x04; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = 0x0000; - fadt->pm_tmr_blk = pm_base+0x08; - fadt->gpe0_blk = pm_base+0x20; - fadt->gpe1_blk = pm_base+0xb0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - fadt->gpe1_blk_len = 8; - fadt->gpe1_base = 16; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state - fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state - fadt->flush_size = 0; // ignored if wbindv = 1 in flags - fadt->flush_stride = 0; // ignored if wbindv = 1 in flags - fadt->duty_offset = 1; - fadt->duty_width = 3; // 0 means duty cycle not supported - // _alrm value 0 means RTC alarm feature not supported - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = - ACPI_FADT_LEGACY_DEVICES | - ACPI_FADT_8042 | - // ACPI_FADT_VGA_NOT_PRESENT | - // ACPI_FADT_MSI_NOT_SUPPORTED| - // ACPI_FADT_NO_PCIE_ASPM_CONTROL| - 0; - - fadt->res2 = 0; - - fadt->flags = - ACPI_FADT_WBINVD | - // ACPI_FADT_WBINVD_FLUSH | - ACPI_FADT_C1_SUPPORTED | - // ACPI_FADT_C2_MP_SUPPORTED | - // ACPI_FADT_POWER_BUTTON | - ACPI_FADT_SLEEP_BUTTON | - // ACPI_FADT_FIXED_RTC | - // ACPI_FADT_S4_RTC_WAKE | - // ACPI_FADT_32BIT_TIMER | - // ACPI_FADT_DOCKING_SUPPORTED| - // ACPI_FADT_RESET_REGISTER | - // ACPI_FADT_SEALED_CASE | - // ACPI_FADT_HEADLESS | - // ACPI_FADT_SLEEP_TYPE | - // ACPI_FADT_PCI_EXPRESS_WAKE | - // ACPI_FADT_PLATFORM_CLOCK | - // ACPI_FADT_S4_RTC_VALID | - // ACPI_FADT_REMOTE_POWER_ON | - // ACPI_FADT_APIC_CLUSTER | - // ACPI_FADT_APIC_PHYSICAL | - 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - - fadt->res3 = 0; - fadt->res4 = 0; - fadt->res5 = 0; - - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pm_base; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pm_base+4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pm_base+0x08; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pm_base+0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 64; - fadt->x_gpe1_blk.bit_offset = 16; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = pm_base+0xb0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - -} diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c deleted file mode 100644 index ef768245ad..0000000000 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * Subject to the GNU GPL v2, or (at your option) any later version. - */ -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/multicore.h> - -#include <cpu/amd/amdk8_sysconf.h> -#include <stdlib.h> - -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 -}; -static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -}; - - -static unsigned get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - - unsigned apicid_base; - - struct device *dev; - int i; - - if (get_bus_conf_done == 1) - return; //do it only once - - get_bus_conf_done = 1; - - sysconf.mb = &mb_sysconf; - struct mb_sysconf_t *m = sysconf.mb; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn3 = sysconf.hcdn[0] & 0xff; - - m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; - m->bus_8111_0 = m->bus_8131_0; - - /* 8111 */ - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) - m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - else - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); - - /* 8131-1 */ - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); - if (dev) - m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - else - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); - - /* 8131-2 */ - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); - if (dev) - m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - else - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); - - -/*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(3); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - m->apicid_8111 = apicid_base+0; - m->apicid_8131_1 = apicid_base+1; - m->apicid_8131_2 = apicid_base+2; -} diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c deleted file mode 100644 index 597acca7e6..0000000000 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ /dev/null @@ -1,98 +0,0 @@ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -#include <cpu/amd/amdk8_sysconf.h> -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - struct mb_sysconf_t *m = sysconf.mb; - - uint8_t sum = 0; - int i; - - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_8111_0; - pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1022; - pirq->rtr_device = 0x746b; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; -//pci bridge - write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; - - pirq_info++; - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h deleted file mode 100644 index 3dfd5deb01..0000000000 --- a/src/mainboard/hp/dl145_g1/mb_sysconf.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * Subject to the GNU GPL v2, or (at your option) any later version. - */ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_8131_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_0; - unsigned char bus_8111_1; - - unsigned apicid_8111; - unsigned apicid_8131_1; - unsigned apicid_8131_2; - - unsigned sbdn3; -}; - -#endif diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c deleted file mode 100644 index 80ad79d7a0..0000000000 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * Subject to the GNU GPL v2, or (at your option) any later version. - */ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/amdk8_sysconf.h> -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - - struct mb_sysconf_t *m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR); - { - struct device *dev; - struct resource *res; - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8131_1, 0x20, - res2mmio(res, 0, 0)); - } - } - dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8131_2, 0x20, - res2mmio(res, 0, 0)); - } - } - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); - - // - // The commented-out lines are auto-detected on my servers. - // -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - // Integrated SMBus 2.0 - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); - // Integrated AMD AC97 Audio - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); - // Integrated AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); - // On board ATI Rage XL - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); - // On board Broadcom nics - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); - // On board LSI SCSI - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); - - // PCIX-133 Slot - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c deleted file mode 100644 index 65a4610d15..0000000000 --- a/src/mainboard/hp/dl145_g1/resourcemap.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * DL145G1 needs a different resource map - * This file was originally copied from the tyan/s2881 coreboot mainboard. - * - * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * Subject to the GNU GPL v2, or (at your option) any later version. - */ - -static void setup_dl145g1_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - //PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - //PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - }; - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c deleted file mode 100644 index e991dc6bda..0000000000 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2011,2014 Oskar Enoksson <enok@lysator.liu.se> - * Subject to the GNU GPL v2, or (at your option) any later version. - */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include <delay.h> -#include <northbridge/amd/amdk8/amdk8.h> -#include "southbridge/amd/amd8111/early_smbus.c" -#include <northbridge/amd/amdk8/raminit.h> - -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <northbridge/amd/amdk8/pre_f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -unsigned get_sbdn(unsigned bus); - -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - /* Set the memreset low. */ - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16); - /* Ensure the BIOS has control of the memory lines. */ - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); - } else { - /* Ensure the CPU has control of the memory lines. */ - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17); - } -} - -void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset high. */ - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); - udelay(90); - } -} - -#define SMBUS_HUB 0x18 - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret != 0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); -} - -static inline void change_i2c_mux(unsigned device) -{ - int ret, i; - printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device); - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret); - } while ((ret != 0) && (i-->0)); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); -} - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "southbridge/amd/amd8111/early_ctrl.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" -#include "resourcemap.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/dualcore/dualcore.c" -#include <spd.h> -#include "cpu/amd/model_fxx/init_cpus.c" -#if IS_ENABLED(CONFIG_SET_FIDVID) -#include "cpu/amd/model_fxx/fidvid.c" -#endif - -#define RC0 ((1 << 1)<<8) -#define RC1 ((1 << 2)<<8) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr [] = { - //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, -#endif - }; - struct sys_info *sysinfo = &sysinfo_car; - - int needs_reset = 0; - unsigned bsp_apicid = 0; - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - - setup_dl145g1_resource_map(); - - setup_coherent_ht_domain(); - wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); -#endif - - ht_setup_chains_x(sysinfo); -#if IS_ENABLED(CONFIG_SET_FIDVID) - /* Check to see if processor is capable of changing FIDVID */ - /* otherwise it will throw a GP# when reading FIDVID_STATUS */ - struct cpuid_result cpuid1 = cpuid(0x80000007); - if ((cpuid1.edx & 0x6) == 0x6) { - { - /* Read FIDVID_STATUS */ - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - - } else { - printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); - } -#endif - - needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } - - enable_smbus(); - - int i; - for (i = 0; i < 2; i++) - activate_spd_rom(&sysinfo->ctrl[i]); - for (i = RC0; i <= RC1; i <<= 1) - change_i2c_mux(i); - - allow_all_aps_stop(bsp_apicid); - - //It's the time to set ctrl now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - memreset_setup(); -#if IS_ENABLED(CONFIG_SET_FIDVID) - init_timer(); // Need to use TMICT to synchronize FID/VID -#endif - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - -} diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig deleted file mode 100644 index da20fb339e..0000000000 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -if BOARD_HP_DL145_G3 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_F - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_BROADCOM_BCM21000 - select SOUTHBRIDGE_BROADCOM_BCM5785 - select HT_CHAIN_DISTRIBUTE - select SUPERIO_SERVERENGINES_PILOT - select SUPERIO_NSC_PC87417 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_512 - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select QRANK_DIMM_SUPPORT - select K8_ALLOCATE_IO_RANGE - select SET_FIDVID - -config MAINBOARD_DIR - string - default hp/dl145_g3 - -config DCACHE_RAM_BASE - hex - default 0xcc000 - -config DCACHE_RAM_SIZE - hex - default 0x04000 - -config APIC_ID_OFFSET - hex - default 0x8 - -config MAINBOARD_PART_NUMBER - string - default "ProLiant DL145 G3" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x6 - -config IRQ_SLOT_COUNT - int - default 15 - -endif # BOARD_HP_DL145_G3 diff --git a/src/mainboard/hp/dl145_g3/Kconfig.name b/src/mainboard/hp/dl145_g3/Kconfig.name deleted file mode 100644 index ebbc20fb94..0000000000 --- a/src/mainboard/hp/dl145_g3/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_DL145_G3 - bool "ProLiant DL145 G3" diff --git a/src/mainboard/hp/dl145_g3/board_info.txt b/src/mainboard/hp/dl145_g3/board_info.txt deleted file mode 100644 index f6f701d4f5..0000000000 --- a/src/mainboard/hp/dl145_g3/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: server -Board URL: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 -Release year: 2007 diff --git a/src/mainboard/hp/dl145_g3/cmos.layout b/src/mainboard/hp/dl145_g3/cmos.layout deleted file mode 100644 index 56ed652b97..0000000000 --- a/src/mainboard/hp/dl145_g3/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb deleted file mode 100644 index b7f450ec06..0000000000 --- a/src/mainboard/hp/dl145_g3/devicetree.cb +++ /dev/null @@ -1,85 +0,0 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end - device domain 0 on - chip northbridge/amd/amdk8 # northbridge - device pci 18.0 on # devices on link 0 - chip southbridge/broadcom/bcm21000 # HT2100 - device pci 0.0 on - end # bridge to slot PCI-E 4x ?? - device pci 1.0 on - end - device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? - end - device pci 4.0 on - end # unused - device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC - end - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.3 off # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA - end - end - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # amdk8 - - end #domain -end diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c deleted file mode 100644 index fc9c104a6c..0000000000 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. - * - * Copyright (C) 2006 MSI - * Written by bxshi <bingxunshi@gmail.com> for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/multicore.h> - -#include <cpu/amd/amdk8_sysconf.h> - -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -static unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 -}; -static unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -}; - - - -static unsigned get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - - unsigned apicid_base; - - struct device *dev; - int i; - struct mb_sysconf_t *m; - - if (get_bus_conf_done == 1) - return; //do it only once - - get_bus_conf_done = 1; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 - - m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff; - m->bus_bcm5780[0] = m->bus_bcm5785_0; - - /* bcm5785 */ - printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0); - dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); - if (dev) { - printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev)); - m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1); - dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); - printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev)); - if (dev) - m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); - } - - /* bcm5780 */ - for (i = 1; i < 6; i++) { - dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); - if (dev) - m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - else - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1); - } - - -/*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(3); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - for (i = 0; i < 3; i++) - m->apicid_bcm5785[i] = apicid_base+i; -} diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c deleted file mode 100644 index 6ec1fd8e79..0000000000 --- a/src/mainboard/hp/dl145_g3/irq_tables.c +++ /dev/null @@ -1,49 +0,0 @@ -#ifdef GETPIR -#include "pirq_routing.h" -#else -#include <arch/pirq_routing.h> -#endif - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x0, /* Where the interrupt router lies (bus) */ - (0x2 << 3)|0x4, - 0, /* IRQs devoted exclusively to PCI usage */ - 0, /* Vendor */ - 0, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x2a, /* u8 checksum. This has to be set to some - value that would give 0 after the sum of all - bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge - {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb - {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr - {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge - {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA - {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge - //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, - {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet - {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, - {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/hp/dl145_g3/mb_sysconf.h b/src/mainboard/hp/dl145_g3/mb_sysconf.h deleted file mode 100644 index 8b0e580057..0000000000 --- a/src/mainboard/hp/dl145_g3/mb_sysconf.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_bcm5780[7]; - unsigned char bus_bcm5785_0; - unsigned char bus_bcm5785_1; - unsigned char bus_bcm5785_1_1; - unsigned apicid_bcm5785[3]; - - unsigned sbdn2; -}; - -#endif diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c deleted file mode 100644 index a6cdfb83d0..0000000000 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com> - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/io.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) -#include <cpu/amd/multicore.h> -#endif -#include <cpu/amd/amdk8_sysconf.h> -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct mb_sysconf_t *m; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - - /*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev = NULL; - int i; - struct resource *res; - for (i = 0; i < 3; i++) { - dev = dev_find_device(0x1166, 0x0235, dev); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base); - smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, - res2mmio(res, 0, 0)); - } - } - } - - } - - /* IRQ routing as factory BIOS */ - outb(0x01, 0xc00); outb(0x0A, 0xc01); - outb(0x17, 0xc00); outb(0x05, 0xc01); -/* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */ -/* outb(0x07, 0xc00); outb(0x07, 0xc01); */ - outb(0x07, 0xc00); outb(0x0b, 0xc01); - - outb(0x24, 0xc00); outb(0x05, 0xc01); - //outb(0x00, 0xc00); outb(0x09, 0xc01); - outb(0x02, 0xc00); outb(0x0E, 0xc01); - - // 8259 registers... - outb(0xa0, 0x4d0); - outb(0x0e, 0x4d1); - - { - struct device *dev; - dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 - pci_write_config32(dev, 0x64, dword); - } - // set GEVENT pins to NO OP - outb(0x33, 0xcd6); outb(0x00, 0xcd7); - outb(0x34, 0xcd6); outb(0x00, 0xcd7); - outb(0x35, 0xcd6); outb(0x00, 0xcd7); - } - - // hide XIOAPIC PCI configuration space - { - struct device *dev; - dev = dev_find_device(0x1166, 0x205, 0); - if (dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x64); - dword |= (1 << 26); - pci_write_config32(dev, 0x64, dword); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); - - //SATA -/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ -/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */ - printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb); - //USB - printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa); - - //VGA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7); - - //PCIE - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe); - - //IDE -// outb(0x02, 0xc00); outb(0x0e, 0xc01); -// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); -// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe); - - //onboard Broadcom GbE - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4); - - - - /* enable int */ - /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ - { - struct device *dev; - dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x6c); - dword |= (1 << 4); // enable interrupts - printk(BIOS_DEBUG, "6ch: %x\n",dword); - pci_write_config32(dev, 0x6c, dword); - } - } - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa); - mptable_lintsrc(mc, bus_isa); - - //extended table entries - smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); - smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); - smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); - smp_write_bus_hierarchy(mc, 9, 0x01, 0); - smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); - smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); - - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c deleted file mode 100644 index 1b25e8cd90..0000000000 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Tyan - * Copyright (C) 2006 AMD - * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include "southbridge/broadcom/bcm5785/early_smbus.c" -#include <northbridge/amd/amdk8/raminit.h> -#include <delay.h> -#include <cpu/x86/lapic.h> -#include <superio/serverengines/pilot/pilot.h> -#include <superio/nsc/pc87417/pc87417.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> - -#include "northbridge/amd/amdk8/setup_resource_map.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) - -unsigned get_sbdn(unsigned bus); - -void memreset(int controllers, const struct mem_controller *ctrl) { } - -void activate_spd_rom(const struct mem_controller *ctrl) -{ -#define SMBUS_SWITCH1 0x70 -#define SMBUS_SWITCH2 0x72 - unsigned device = (ctrl->channel0[0]) >> 8; - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); -} - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "southbridge/broadcom/bcm5785/early_setup.c" -#include <northbridge/amd/amdk8/f.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "lib/generic_sdram.c" -#include <spd.h> -#include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" - -#if 0 -#include "ipmi.c" - -static void setup_early_ipmi_serial() -{ - unsigned char result; - char channel_access[]={0x06 << 2,0x40,0x04,0x80,0x05}; - char serialmodem_conf[]={0x0c << 2,0x10,0x04,0x08,0x00,0x0f}; - char serial_mux1[]={0x0c << 2,0x12,0x04,0x06}; - char serial_mux2[]={0x0c << 2,0x12,0x04,0x03}; - char serial_mux3[]={0x0c << 2,0x12,0x04,0x07}; - -// earlydbg(0x0d); - //set channel access system only - ipmi_request(5,channel_access); -// earlydbg(result); -/* - //Set serial/modem config - result = ipmi_request(6,serialmodem_conf); - earlydbg(result); - - //Set serial mux 1 - result = ipmi_request(4,serial_mux1); - earlydbg(result); - - //Set serial mux 2 - result = ipmi_request(4,serial_mux2); - earlydbg(result); - - //Set serial mux 3 - result = ipmi_request(4,serial_mux3); - earlydbg(result); -*/ -// earlydbg(0x0e); - -} -#endif - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr[] = { - // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, - }; - - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - bcm5785_enable_lpc(); - pc87417_enable_dev(RTC_DEV); /* Enable RTC */ - } - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - -// setup_early_ipmi_serial(); - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); - - wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); -#endif - - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - bcm5785_early_setup(); - -#if IS_ENABLED(CONFIG_SET_FIDVID) - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); - } -#endif - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - - allow_all_aps_stop(bsp_apicid); - - //It's the time to set ctrl in sysinfo now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); - - //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - // init_timer(); // Need to use TMICT to synchronize FID/VID - - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -} |