diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-16 23:29:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:00:57 +0000 |
| commit | 6beaef983aee5d886f6f8571855a92d608d98a17 (patch) | |
| tree | 9c7f858bc7baa36d9e18ed84ea61d742559922c2 /src/mainboard/hp/folio_9470m | |
| parent | 4821a0e135ff2d60f552203d2724ae2d44850623 (diff) | |
sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/hp/folio_9470m')
| -rw-r--r-- | src/mainboard/hp/folio_9470m/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/hp/folio_9470m/romstage.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 5d4e5b8ea2..d626934343 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" register "gen3_dec" = "0x00fcfe01" diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index db3296c457..8ff7813cd9 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -30,8 +30,6 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); } void mainboard_rcba_config(void) |