src/mainboard/getac - kontron: Add space around operators

Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 19 insertions, 19 deletions

diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index e32387386b..68c38813dc 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -69,7 +69,7 @@ void get_bus_conf(void)
 	int i;
 	struct mb_sysconf_t *m;
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -80,7 +80,7 @@ void get_bus_conf(void)
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
 
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -124,6 +124,6 @@ void get_bus_conf(void)
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	apicid_base = 0x10;
-	for(i=0;i<3;i++)
+	for(i = 0; i < 3; i++)
 		m->apicid_bcm5785[i] = apicid_base+i;
 }
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 395de572c1..17e42e4f44 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
+ * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com>
  *
  * Copyright (C) 2006 AMD
  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
 		device_t dev = 0;
 		int i;
 		struct resource *res;
-		for(i=0; i<3; i++) {
+		for(i = 0; i < 3; i++) {
 			dev = dev_find_device(0x1166, 0x0235, dev);
 			if (dev) {
 				res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
 		if(dev) {
 			uint32_t dword;
 			dword = pci_read_config32(dev, 0x64);
-			dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
+			dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
 			pci_write_config32(dev, 0x64, dword);
 		}
 		// set GEVENT pins to NO OP
@@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v)
 		if (dev) {
 			uint32_t dword;
 			dword = pci_read_config32(dev, 0x64);
-			dword |= (1<<26);
+			dword |= (1 << 26);
 			pci_write_config32(dev, 0x64, dword);
 		}
 	}
@@ -113,16 +113,16 @@ static void *smp_write_config_table(void *v)
 	mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
 
 	/* I/O Ints:		Type	Polarity/Trigger			Bus ID		IRQ	APIC ID		PIN#  */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0,	m->apicid_bcm5785[0], 0x5);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0,	m->apicid_bcm5785[0], 0xa);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0,	m->apicid_bcm5785[2], 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0,	m->apicid_bcm5785[2], 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0,	m->apicid_bcm5785[2], 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0,	m->apicid_bcm5785[2], 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0,	m->apicid_bcm5785[2], 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0,	m->apicid_bcm5785[2], 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1,	m->apicid_bcm5785[2], 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0,	m->apicid_bcm5785[2], 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe << 2)|0,	m->apicid_bcm5785[0], 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3 << 2)|0,	m->apicid_bcm5785[0], 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0,	m->apicid_bcm5785[2], 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0,	m->apicid_bcm5785[2], 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0,	m->apicid_bcm5785[2], 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0,	m->apicid_bcm5785[2], 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0,	m->apicid_bcm5785[2], 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|0,	m->apicid_bcm5785[2], 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|1,	m->apicid_bcm5785[2], 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0 << 2)|0,	m->apicid_bcm5785[2], 0xa);
 
 	/* enable int */
 	/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
@@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v)
 		if(dev) {
 			uint32_t dword;
 			dword = pci_read_config32(dev, 0x6c);
-			dword |= (1<<4); // enable interrupts
+			dword |= (1 << 4); // enable interrupts
 			printk(BIOS_DEBUG, "6ch: %x\n",dword);
 			pci_write_config32(dev, 0x6c, dword);
 		}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 84e28f7fc9..39cd0e339d 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif