diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-02 18:49:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-04 10:05:04 +0000 |
| commit | 6f15ba0112c693c129d0425c19af4de6b9231f8a (patch) | |
| tree | 2068d50ef3bfe8b30e11a8156544c9cb456fd8ac /src/mainboard/hp/dl145_g1/romstage.c | |
| parent | 8f1e03920f55a508f835e51ddabe179684e12bee (diff) | |
mainboard/hp/dl145_g1: Remove commented code
Change-Id: I4528eb064e8b9c5ebb235ca16e13582df9efd4cd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/hp/dl145_g1/romstage.c')
| -rw-r--r-- | src/mainboard/hp/dl145_g1/romstage.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 1ef3658a62..e991dc6bda 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -125,7 +125,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_dl145g1_resource_map(); - //setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); @@ -180,10 +179,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) for (i = RC0; i <= RC1; i <<= 1) change_i2c_mux(i); - //dump_spd_registers(&sysinfo->ctrl[0]); - //dump_spd_registers(&sysinfo->ctrl[1]); - //dump_smbus_registers(); - allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl now; |