hp/dl145_g1: Adding ACPI support

Basic ACPI support for this old platform. Created by copying and
tweaking similar motherboard ACPI implementations in coreboot.
Works reasonably well under Linux, providing HPET-timers
and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44).
Not tested under Windows.

Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5185
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

5 files changed, 1110 insertions, 0 deletions

diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
new file mode 100644
index 0000000000..aa136ffbf2
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
@@ -0,0 +1,617 @@
+/*
+ * Copyright 2005 AMD
+ * Copyright (C) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se>
+ */
+//AMD8111
+// APIC version of the interrupt routing table
+Name (APIC, Package (0x04) {
+	Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+	Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+	Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+	Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+})
+// PIC version of the interrupt routing table
+Name (PICM, Package (0x04) {
+	Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+	Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+	Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+	Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
+})
+Name (DNCG, Ones)
+Method (_PRT, 0, NotSerialized) {
+	If (LEqual (^DNCG, Ones)) {
+		Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+		// Update the Device Number according to SBDN
+		Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+		Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+		Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+		Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+
+		Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+		Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+		Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+		Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+
+		Store (0x00, ^DNCG)
+	}
+
+	If (LNot (PICF)) {
+		Return (PICM)
+	} Else {
+		Return (APIC)
+	}
+}
+
+// AMD8111 System Management I/O Mapped Registers (PMxx)
+OperationRegion (PMIO, SystemIO, PMBS, 0xDF)
+Field (PMIO, ByteAcc, NoLock, Preserve) {
+					Offset (0x1E),
+	SWSM,   8,  // Software SMI Trigger (sets GSTS)
+					Offset (0x28),
+	GSTS,   16, // Global STatuS
+	GNBL,   16, // Global SMI enable
+					Offset (0x30),
+	STMC,   5,  // Miscellaneous SMI Status
+					Offset (0x32),
+	ENMC,   5,  // Miscellaneous SMI Enable
+					Offset (0x44),
+	STC0,   9,  // TCO Status 1
+					Offset (0x46),
+	STC1,   4,  // TCO Status 2
+					Offset (0xA8),
+	STHW,   20  // Device monitor SMI Interrupt Enable
+}
+Device (HPET) {
+	Name (HPT, 0x00)
+	Name (_HID, EisaId ("PNP0103"))
+	Name (_UID, 0x00)
+	Method (_STA, 0, NotSerialized) {
+		Return (0x0F)
+	}
+	Method (_CRS, 0, Serialized) {
+		Name (BUF0, ResourceTemplate () {
+			Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+		})
+		Return (BUF0)
+	}
+}
+#include "amd8111_pic.asl"
+#include "amd8111_isa.asl"
+
+Device (TP2P) {
+	// 8111 P2P and it should 0x00030000 when 8131 present
+	Method (_ADR, 0, NotSerialized) {
+		Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+	}
+	Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+	// result :
+	// [0] Bit index into GPEx_EN in the GPE block described by FADT.
+	// [1] The lowest power state from which the system can be awakened.
+		//If (CondRefOf (\_S3, Local0)) {
+		//	Return (Package (0x02) { 0x08, 0x03 })
+		//} Else {
+			Return (Package (0x02) { 0x08, 0x01 })
+		//}
+	}
+	Device (ETHR) {
+		Name (_ADR, 0x00010000)
+		Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+			//If (CondRefOf (\_S3, Local0)) {
+			//	Return (Package (0x02) { 0x08, 0x03 })
+			//} Else {
+				Return (Package (0x02) { 0x08, 0x01 })
+			//}
+		}
+	}
+	Device (USB0) {
+		Name (_ADR, 0x00000000)
+		Method (_PSW, 1, NotSerialized) { // Power State Wake
+			And (GNBL, 0x7FFF, GNBL)
+		}
+		Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+			//If (CondRefOf (\_S3, Local0)) {
+			//	Return (Package (0x02) { 0x0F, 0x03 })
+			//} Else {
+				Return (Package (0x02) { 0x0F, 0x01 })
+			//}
+		}
+	}
+	Device (USB1) {
+		Name (_ADR, 0x00000001)
+		Method (_PSW, 1, NotSerialized) { // Power State Wake
+			And (GNBL, 0x7FFF, GNBL)
+		}
+		Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+			//If (CondRefOf (\_S3, Local0)) {
+			//	Return (Package (0x02) { 0x0F, 0x03 })
+			//} Else {
+				Return (Package (0x02) { 0x0F, 0x01 })
+			//}
+		}
+	}
+	Name (APIC, Package (0x0C) {
+		Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+		Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+		Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+		Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+		Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
+		Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+		Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+		Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+		Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
+		Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+		Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+		Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+	})
+	Name (PICM, Package (0x0C) {
+		Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+		Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+		Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
+		Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+		Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+		Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
+		Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+	})
+	Method (_PRT, 0, NotSerialized) {
+		If (LNot (PICF)) { Return (PICM) }
+		Else             { Return (APIC) }
+	}
+}
+Device (IDE0) {
+	Method (_ADR, 0, NotSerialized) {
+		Return (DADD(\_SB.PCI0.SBDN, 0x00010001))
+	}
+	Name (REGF, 0x01)
+	Method (_REG, 2, NotSerialized) {
+		If (LEqual (Arg0, 0x02)) {
+			Store (Arg1, REGF)
+		}
+	}
+	OperationRegion (BAR0, PCI_Config, 0x00, 0x60)
+	Field (BAR0, ByteAcc, NoLock, Preserve) {
+						Offset (0x40), // EIDE Controller Configuration Register
+		SCEN,   1,  // Secondary Channel Enable
+		PCEN,   1,  // Primary Channel Enable
+				,   10,
+		SPWB,   1,  // Secondary Port posted-write buffer for PIO modes enable
+		SRPB,   1,  // RW (controls nothing)
+		PPWB,   1,  // Primary Port posted-write buffer for PIO modes enable
+		PRPB,   1,  // RW (controls nothing)
+		PM80,   1,  // High-speed 80-pin cable enable Primary Master
+		PS80,   1,  // High-speed 80-pin cable enable Primary Slave
+		SM80,   1,  // High-speed 80-pin cable enable Secondary Master
+		SS80,   1,  // High-speed 80-pin cable enable Secondary Slave
+				,   4,  // RW (controls nothing)
+						Offset (0x48),
+		SSRT,   4,  //
+		SSPW,   4,  //
+		SMRT,   4,  //
+		SMPW,   4,
+		PSRT,   4,
+		PSPW,   4,
+		PMRT,   4,
+		PMPW,   4,
+		SSAD,   2,
+		SMAD,   2,
+		PSAD,   2,
+		PMAD,   2,
+						Offset (0x4E),
+		SXRT,   4,
+		SXPW,   4,
+		PXRT,   4,
+		PXPW,   4,
+		SSUD,   8,
+		SMUD,   8,
+		PSUD,   8,
+		PMUD,   8,
+		PPDN,   1,
+		PPDS,   1,
+				,   2,
+		SPDN,   1,
+		SPDS,   1
+	}
+	Name (TIM0, Package (0x06) {
+		Package (0x05) {
+			0x78,
+			0xB4,
+			0xF0,
+			0x0186,
+			0x0258
+		},
+		Package (0x07) {
+			0x78,
+			0x5A,
+			0x3C,
+			0x2D,
+			0x1E,
+			0x14,
+			0x0F
+		},
+		Package (0x08) {
+			0x04,
+			0x03,
+			0x02,
+			0x01,
+			0x00,
+			0x00,
+			0x00,
+			0x00
+		},
+		Package (0x03) {
+			0x02,
+			0x01,
+			0x00
+		},
+		Package (0x05) {
+			0x20,
+			0x22,
+			0x42,
+			0x65,
+			0xA8
+		},
+		Package (0x07) {
+			0xC2,
+			0xC1,
+			0xC0,
+			0xC4,
+			0xC5,
+			0xC6,
+			0xC7
+		}
+	})
+	Name (TMD0, Buffer (0x14) {})
+	CreateDWordField (TMD0, 0x00, PIO0)
+	CreateDWordField (TMD0, 0x04, DMA0)
+	CreateDWordField (TMD0, 0x08, PIO1)
+	CreateDWordField (TMD0, 0x0C, DMA1)
+	CreateDWordField (TMD0, 0x10, CHNF)
+	Device (CHN0) {
+		Name (_ADR, 0x00)
+		Method (_STA, 0, NotSerialized) {
+			If (PCEN) { Return (0x0F) }
+			Else      { Return (0x09) }
+		}
+		Method (_GTM, 0, NotSerialized) {
+			Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD))
+		}
+		Method (_STM, 3, NotSerialized) {
+			Store (Arg0, TMD0)
+			Store (STM (), Local0)
+			And (Local0, 0xFF, PSUD)
+			ShiftRight (Local0, 0x08, Local0)
+			And (Local0, 0xFF, PMUD)
+			ShiftRight (Local0, 0x08, Local0)
+			And (Local0, 0x0F, PSRT)
+			ShiftRight (Local0, 0x04, Local0)
+			And (Local0, 0x0F, PSPW)
+			ShiftRight (Local0, 0x04, Local0)
+			And (Local0, 0x0F, PMRT)
+			ShiftRight (Local0, 0x04, Local0)
+			And (Local0, 0x0F, PMPW)
+			Store (GTF (0x00, Arg1), ATA0)
+			Store (GTF (0x01, Arg2), ATA1)
+		}
+		Device (DRV0) {
+			Name (_ADR, 0x00)
+			Method (_GTF, 0, NotSerialized) {
+				Return (RATA (ATA0))
+			}
+		}
+		Device (DRV1) {
+			Name (_ADR, 0x01)
+			Method (_GTF, 0, NotSerialized) {
+				Return (RATA (ATA1))
+			}
+		}
+	}
+	Device (CHN1) {
+		Name (_ADR, 0x01)
+		Method (_STA, 0, NotSerialized) {
+			If (SCEN) { Return (0x0F) }
+			Else      { Return (0x09) }
+		}
+		Method (_GTM, 0, NotSerialized) {
+			Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD))
+		}
+		Method (_STM, 3, NotSerialized) {
+			Store (Arg0, TMD0)
+			Store (STM (), Local0)
+			And (Local0, 0xFF, SSUD)
+			ShiftRight (Local0, 0x08, Local0)
+			And (Local0, 0xFF, SMUD)
+			ShiftRight (Local0, 0x08, Local0)
+			And (Local0, 0x0F, SSRT)
+			ShiftRight (Local0, 0x04, Local0)
+			And (Local0, 0x0F, SSPW)
+			ShiftRight (Local0, 0x04, Local0)
+			And (Local0, 0x0F, SMRT)
+			ShiftRight (Local0, 0x04, Local0)
+			And (Local0, 0x0F, SMPW)
+			Store (GTF (0x00, Arg1), ATA2)
+			Store (GTF (0x01, Arg2), ATA3)
+		}
+		Device (DRV0) {
+			Name (_ADR, 0x00)
+			Method (_GTF, 0, NotSerialized) {
+				Return (RATA (ATA2))
+			}
+		}
+		Device (DRV1) {
+			Name (_ADR, 0x01)
+			Method (_GTF, 0, NotSerialized) {
+				Return (RATA (ATA3))
+			}
+		}
+	}
+	Method (GTM, 6, Serialized) {
+		Store (Ones, PIO0)
+		Store (Ones, PIO1)
+		Store (Ones, DMA0)
+		Store (Ones, DMA1)
+		Store (0x1A, CHNF)
+		If (REGF) {}
+		Else      { Return (TMD0) }
+		Add (Arg0, Arg1, Local0)
+		Add (Local0, 0x02, Local0)
+		Multiply (Local0, 0x1E, PIO0)
+		Add (Arg2, Arg3, Local0)
+		Add (Local0, 0x02, Local0)
+		Multiply (Local0, 0x1E, PIO1)
+		If (And (Arg4, 0x40)) {
+			Or (CHNF, 0x01, CHNF)
+			And (Arg4, 0x07, Local0)
+			If (LLess (Local0, 0x04)) {
+				Add (Local0, 0x02, Local0)
+				Multiply (Local0, 0x1E, DMA0)
+			} Else {
+				If (LEqual (Local0, 0x04)) {
+					Store (0x2D, DMA0)
+				} Else {
+					If (LEqual (Local0, 0x05)) {
+						Store (0x1E, DMA0)
+					} Else {
+						If (LEqual (Local0, 0x06)) {
+							Store (0x14, DMA0)
+						} Else {
+							If (LEqual (Local0, 0x07)) {
+								Store (0x0F, DMA0)
+							} Else {
+								Store (PIO0, DMA0)
+							}
+						}
+					}
+				}
+			}
+		} Else {
+			Store (PIO0, DMA0)
+		}
+		If (And (Arg5, 0x40)) {
+			Or (CHNF, 0x04, CHNF)
+			And (Arg5, 0x07, Local0)
+			If (LLess (Local0, 0x04)) {
+				Add (Local0, 0x02, Local0)
+				Multiply (Local0, 0x1E, DMA1)
+			} Else {
+				If (LEqual (Local0, 0x04)) {
+					Store (0x2D, DMA1)
+				} Else {
+					If (LEqual (Local0, 0x05)) {
+						Store (0x1E, DMA1)
+					} Else {
+						If (LEqual (Local0, 0x06)) {
+							Store (0x14, DMA1)
+						} Else {
+							If (LEqual (Local0, 0x07)) {
+								Store (0x0F, DMA0)
+							} Else {
+								Store (PIO1, DMA1)
+							}
+						}
+					}
+				}
+			}
+		} Else {
+			Store (PIO1, DMA1)
+		}
+		Return (TMD0)
+	}
+	Method (STM, 0, Serialized) {
+		If (REGF) {}
+		Else      { Return (0xFFFFFFFF) }
+		If (LEqual (PIO0, 0xFFFFFFFF)) {
+			Store (0xA8, Local1)
+		} Else {
+			And (Match (DerefOf (Index (TIM0, 0x00)),
+									MGE, PIO0, MTR,
+									0x00, 0x00),
+					0x07, Local0)
+			Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
+						Local1)
+		}
+		ShiftLeft (Local1, 0x08, Local1)
+		If (LEqual (PIO1, 0xFFFFFFFF)) {
+			Or (Local1, 0xA8, Local1)
+		} Else {
+			And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR,
+									0x00, 0x00), 0x07, Local0)
+			Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
+					Local1, Local1)
+		}
+		ShiftLeft (Local1, 0x08, Local1)
+		If (LEqual (DMA0, 0xFFFFFFFF)) {
+			Or (Local1, 0x03, Local1)
+		} Else {
+			If (And (CHNF, 0x01)) {
+				And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR,
+										0x00, 0x00), 0x07, Local0)
+				Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
+						Local1, Local1)
+			} Else {
+				Or (Local1, 0x03, Local1)
+			}
+		}
+		ShiftLeft (Local1, 0x08, Local1)
+		If (LEqual (DMA1, 0xFFFFFFFF)) {
+			Or (Local1, 0x03, Local1)
+		} Else {
+			If (And (CHNF, 0x04)) {
+				And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR,
+										0x00, 0x00), 0x07, Local0)
+				Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
+						Local1, Local1)
+			} Else {
+				Or (Local1, 0x03, Local1)
+			}
+		}
+		Return (Local1)
+	}
+	Name (AT01, Buffer (0x07) {
+		0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
+	})
+	Name (AT02, Buffer (0x07) {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
+	})
+	Name (AT03, Buffer (0x07) {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
+	})
+	Name (AT04, Buffer (0x07) {
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
+	})
+	Name (ATA0, Buffer (0x1D) {})
+	Name (ATA1, Buffer (0x1D) {})
+	Name (ATA2, Buffer (0x1D) {})
+	Name (ATA3, Buffer (0x1D) {})
+	Name (ATAB, Buffer (0x1D) {})
+	CreateByteField (ATAB, 0x00, CMDC)
+	Method (GTFB, 3, Serialized) {
+		Multiply (CMDC, 0x38, Local0)
+		Add (Local0, 0x08, Local1)
+		CreateField (ATAB, Local1, 0x38, CMDX)
+		Multiply (CMDC, 0x07, Local0)
+		CreateByteField (ATAB, Add (Local0, 0x02), A001)
+		CreateByteField (ATAB, Add (Local0, 0x06), A005)
+		Store (Arg0, CMDX)
+		Store (Arg1, A001)
+		Store (Arg2, A005)
+		Increment (CMDC)
+	}
+	Method (GTF, 2, Serialized) {
+		Store (Arg1, Debug)
+		Store (0x00, CMDC)
+		Name (ID49, 0x0C00)
+		Name (ID59, 0x00)
+		Name (ID53, 0x04)
+		Name (ID63, 0x0F00)
+		Name (ID88, 0x0F00)
+		Name (IRDY, 0x01)
+		Name (PIOT, 0x00)
+		Name (DMAT, 0x00)
+		If (LEqual (SizeOf (Arg1), 0x0200)) {
+			CreateWordField (Arg1, 0x62, IW49)
+			Store (IW49, ID49)
+			CreateWordField (Arg1, 0x6A, IW53)
+			Store (IW53, ID53)
+			CreateWordField (Arg1, 0x7E, IW63)
+			Store (IW63, ID63)
+			CreateWordField (Arg1, 0x76, IW59)
+			Store (IW59, ID59)
+			CreateWordField (Arg1, 0xB0, IW88)
+			Store (IW88, ID88)
+		}
+		Store (0xA0, Local7)
+		If (Arg0) {
+			Store (0xB0, Local7)
+			And (CHNF, 0x08, IRDY)
+			If (And (CHNF, 0x10)) {
+				Store (PIO1, PIOT)
+			} Else {
+				Store (PIO0, PIOT)
+			}
+			If (And (CHNF, 0x04)) {
+				If (And (CHNF, 0x10)) {
+					Store (DMA1, DMAT)
+				} Else {
+					Store (DMA0, DMAT)
+				}
+			} Else {
+				Store (PIO1, DMAT)
+			}
+		} Else {
+			And (CHNF, 0x02, IRDY)
+			Store (PIO0, PIOT)
+			If (And (CHNF, 0x01)) {
+				Store (DMA0, DMAT)
+			}
+		}
+		If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) {
+			Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR,
+										0x00, 0x00), Local1)
+			If (LGreater (Local1, 0x06)) {
+				Store (0x06, Local1)
+			}
+			GTFB (AT01, Or (0x40, Local1), Local7)
+		} Else {
+			If (LAnd (And (ID63, 0xFF00), PIOT)) {
+				And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
+										0x00, 0x00), 0x07, Local0)
+				If (Local0) {
+					If (And (Local0, 0x04)) {
+						Store (0x02, Local0)
+					} Else {
+						Store (0x01, Local0)
+					}
+				}
+				Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
+												)), Local1)
+				GTFB (AT01, Local1, Local7)
+			}
+		}
+		If (IRDY) {
+			And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
+									0x00, 0x00), 0x07, Local0)
+			Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
+											)), Local1)
+			GTFB (AT01, Local1, Local7)
+		} Else {
+			If (And (ID49, 0x0400)) {
+				GTFB (AT01, 0x01, Local7)
+			}
+		}
+		If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) {
+			GTFB (AT03, And (ID59, 0xFF), Local7)
+		}
+		Store (ATAB, Debug)
+		Return (ATAB)
+	}
+	Method (RATA, 1, NotSerialized) {
+		CreateByteField (Arg0, 0x00, CMDN)
+		Multiply (CMDN, 0x38, Local0)
+		CreateField (Arg0, 0x08, Local0, RETB)
+		Store (RETB, Debug)
+		Return (RETB)
+	}
+}
+Device (PMF) {
+	// acpi smbus   it should be 0x00040003 if 8131 present
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+	}
+	OperationRegion (BAR0, PCI_Config, 0x00, 0xff)
+	Field (BAR0, ByteAcc, NoLock, Preserve) {
+						Offset (0x56),
+		PIRA,   4,
+		PIRB,   4,
+		PIRC,   4,
+		PIRD,   4
+	}
+	//OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+	//Field (TS3_, DWordAcc, NoLock, Preserve) {
+	//	PTS3,   16
+	//}
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl
new file mode 100644
index 0000000000..be2a1ffdb4
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2005 AMD
+ * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
+ */
+//AMD8111 isa
+
+Device (ISA) {
+	// lpc  0x00040000
+	Method (_ADR, 0, NotSerialized) {
+		Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+	}
+	/*
+	OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+	Field (PIRY, ByteAcc, NoLock, Preserve) {
+		Z000,   2,  // Parallel Port Range
+				,   1,
+		ECP ,   1,  // ECP Enable
+		FDC1,   1,  // Floppy Drive Controller 1
+		FDC2,   1,  // Floppy Drive Controller 2
+						Offset (0x01),
+		Z001,   3,  // Serial Port A Range
+		SAEN,   1,  // Serial Post A Enabled
+		Z002,   3,  // Serial Port B Range
+		SBEN,   1   // Serial Post B Enabled
+	}
+	*/
+	Device (PIC) {
+		Name (_HID, EisaId ("PNP0000"))
+		Name (_CRS, ResourceTemplate () {
+			IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)  // Master Interrupt controller
+			IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)  // Slave Interrupt controller
+			IRQ (Edge, ActiveHigh, Exclusive) {2}
+		})
+	}
+	Device (DMA1) {
+	Name (_HID, EisaId ("PNP0200"))
+		Name (_CRS, ResourceTemplate () {
+			IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)  // Slave DMA controller
+			IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)  // DMA page registers
+			IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)  // Master DMA controller
+			DMA (Compatibility, NotBusMaster, Transfer16) {4}
+		})
+	}
+	Device (TMR) {
+		Name (_HID, EisaId ("PNP0100"))
+		Name (_CRS, ResourceTemplate () {
+			IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)  // Programmable Interval timer
+			IRQ (Edge, ActiveHigh, Exclusive) {0}
+		})
+	}
+	Device (RTC) {
+		Name (_HID, EisaId ("PNP0B00"))
+		Name (_CRS, ResourceTemplate () {
+			IO (Decode16, 0x0070, 0x0070, 0x01, 0x04)  // Realtime Clock and CMOS ram
+			IRQ (Edge, ActiveHigh, Exclusive) {8}
+		})
+	}
+	Device (SPKR) {
+		Name (_HID, EisaId ("PNP0800"))
+		Name (_CRS, ResourceTemplate () {
+			IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)  // PC speaker
+		})
+	}
+	Device (COPR) { // Co-processor
+		Name (_HID, EisaId ("PNP0C04"))
+		Name (_CRS, ResourceTemplate () {
+			IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)  // Floating point Error control
+			IRQ (Edge, ActiveHigh, Exclusive) {13}
+		})
+	}
+	Device (SYSR) {  // System control registers (?)
+		Name (_HID, EisaId ("PNP0C02"))
+		Name (_UID, 0x00)
+		Name (CRS, ResourceTemplate () {
+			IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+			IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+			IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+			IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+			IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+			IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C)
+			IO (Decode16, 0x0080, 0x0080, 0x01, 0x01)
+			IO (Decode16, 0x0084, 0x0084, 0x01, 0x03)
+			IO (Decode16, 0x0088, 0x0088, 0x01, 0x01)
+			IO (Decode16, 0x008C, 0x008C, 0x01, 0x03)
+			IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+			IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+			IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+			// IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+			// EISA defined level triggered interrupt control registers
+			IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02)
+			// IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+			// IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80)
+			// IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80)
+			IO (Decode16,0xDE00,0xDE00,0x00,0x80)
+			IO (Decode16,0xDE80,0xDE80,0x00,0x80)
+			// IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
+			// IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+			IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block
+			IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block
+			IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block
+		})
+		Method (_CRS, 0, NotSerialized) {
+			CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00)
+			CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01)
+			CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L)
+			Store (PMBS, GP00)
+			Store (PMBS, GP01)
+			Store (PMLN, GP0L)
+			If (SMBS) {
+				CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10)
+				CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11)
+				CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L)
+				Store (SMBS, GP10)
+				Store (SMBS, GP11)
+				Store (SMBL, GP1L)
+			}
+			If (GPBS) {
+				CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20)
+				CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21)
+				CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L)
+				Store (GPBS, GP20)
+				Store (GPBS, GP21)
+				Store (GPLN, GP2L)
+			}
+			Return (CRS)
+		}
+	}
+	Device (MEM) {
+		Name (_HID, EisaId ("PNP0C02"))
+		Name (_UID, 0x01)
+		Method (_CRS, 0, Serialized) {
+			Name (BUF0, ResourceTemplate () {
+				Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+				Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
+				Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+				Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+				Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+				Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+				Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+				Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+				Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+				Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+			})
+// Read the Video Memory length
+			CreateDWordField (BUF0, 0x14, CLEN)
+			CreateDWordField (BUF0, 0x10, CBAS)
+
+			ShiftLeft (VGA1, 0x09, Local0)
+			Store (Local0, CLEN)
+
+			Return (BUF0)
+		}
+	}
+#include "superio/winbond/w83627hf/acpi/superio.asl"
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl
new file mode 100644
index 0000000000..a09c576102
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2005 AMD
+ * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
+ */
+//AMD8111 pic LNKA B C D
+
+Device (LNKA) {
+	Name (_HID, EisaId ("PNP0C0F"))
+	Name (_UID, 0x01)
+	Method (_STA, 0, NotSerialized)	{
+		If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled
+		Else                                    { Return (0x0B) } //Enabled
+	}
+	Method (_PRS, 0, Serialized)	{
+		Name (BUFA, ResourceTemplate ()	{
+			IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+		})
+		Return (BUFA)
+	}
+	Method (_DIS, 0, NotSerialized) {
+		Store (0x00, \_SB.PCI0.PMF.PIRA )
+	}
+
+	Method (_CRS, 0, Serialized) {
+		Name (BUFA, ResourceTemplate ()	{
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateByteField (BUFA, 0x01, IRA1)
+		CreateByteField (BUFA, 0x02, IRA2)
+		Store (0x00, Local2)
+		Store (0x00, Local3)
+		Store (\_SB.PCI0.PMF.PIRA, Local1)
+		If (LNot (LEqual (Local1, 0x00))) {  // Routing enable
+			If (LGreater (Local1, 0x07)) {
+				Subtract (Local1, 0x08, Local1)
+				ShiftLeft (One, Local1, Local3)
+			} Else {
+				If (LGreater (Local1, 0x00)) {
+					ShiftLeft (One, Local1, Local2)
+				}
+			}
+			Store (Local2, IRA1)
+			Store (Local3, IRA2)
+		}
+		Return (BUFA)
+	}
+
+	Method (_SRS, 1, NotSerialized) {
+		CreateByteField (Arg0, 0x01, IRA1)
+		CreateByteField (Arg0, 0x02, IRA2)
+		ShiftLeft (IRA2, 0x08, Local0)
+		Or (Local0, IRA1, Local0)
+		Store (0x00, Local1)
+		ShiftRight (Local0, 0x01, Local0)
+		While (LGreater (Local0, 0x00)) {
+			Increment (Local1)
+			ShiftRight (Local0, 0x01, Local0)
+		}
+		Store(Local1,\_SB.PCI0.PMF.PIRA)
+	}
+}
+
+Device (LNKB) {
+	Name (_HID, EisaId ("PNP0C0F"))
+	Name (_UID, 0x02)
+	Method (_STA, 0, NotSerialized) {
+		If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled
+		Else                                    { Return (0x0B) } //Enabled
+	}
+
+	Method (_PRS, 0, Serialized) {
+		Name (BUFB, ResourceTemplate () {
+			IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+		})
+		Return (BUFB)
+	}
+
+	Method (_DIS, 0, NotSerialized) {
+		Store (0x00, \_SB.PCI0.PMF.PIRB )
+	}
+
+	Method (_CRS, 0, Serialized) {
+		Name (BUFB, ResourceTemplate () {
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateByteField (BUFB, 0x01, IRA1)
+		CreateByteField (BUFB, 0x02, IRA2)
+		Store (0x00, Local2)
+		Store (0x00, Local3)
+		Store (\_SB.PCI0.PMF.PIRB, Local1)
+		If (LNot (LEqual (Local1, 0x00))) {  // Routing enable
+			If (LGreater (Local1, 0x07)) {
+				Subtract (Local1, 0x08, Local1)
+				ShiftLeft (One, Local1, Local3)
+			} Else {
+				If (LGreater (Local1, 0x00)) {
+					ShiftLeft (One, Local1, Local2)
+				}
+			}
+			Store (Local2, IRA1)
+			Store (Local3, IRA2)
+		}
+		Return (BUFB)
+	}
+
+	Method (_SRS, 1, NotSerialized) {
+		CreateByteField (Arg0, 0x01, IRA1)
+		CreateByteField (Arg0, 0x02, IRA2)
+		ShiftLeft (IRA2, 0x08, Local0)
+		Or (Local0, IRA1, Local0)
+		Store (0x00, Local1)
+		ShiftRight (Local0, 0x01, Local0)
+		While (LGreater (Local0, 0x00)) {
+			Increment (Local1)
+			ShiftRight (Local0, 0x01, Local0)
+		}
+		Store(Local1,\_SB.PCI0.PMF.PIRB)
+	}
+}
+
+Device (LNKC) {
+	Name (_HID, EisaId ("PNP0C0F"))
+	Name (_UID, 0x03)
+	Method (_STA, 0, NotSerialized) {
+		If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled
+		Else                                    { Return (0x0B) } //Enabled
+	}
+
+	Method (_PRS, 0, Serialized) {
+		Name (BUFA, ResourceTemplate () {
+			IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+		})
+		Return (BUFA)
+	}
+
+	Method (_DIS, 0, NotSerialized) {
+		Store (0x00, \_SB.PCI0.PMF.PIRC )
+	}
+
+	Method (_CRS, 0, Serialized) {
+		Name (BUFA, ResourceTemplate () {
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateByteField (BUFA, 0x01, IRA1)
+		CreateByteField (BUFA, 0x02, IRA2)
+		Store (0x00, Local2)
+		Store (0x00, Local3)
+		Store (\_SB.PCI0.PMF.PIRC, Local1)
+		If (LNot (LEqual (Local1, 0x00))) {  // Routing enable
+			If (LGreater (Local1, 0x07)) {
+				Subtract (Local1, 0x08, Local1)
+				ShiftLeft (One, Local1, Local3)
+			} Else {
+				If (LGreater (Local1, 0x00)) {
+					ShiftLeft (One, Local1, Local2)
+				}
+			}
+			Store (Local2, IRA1)
+			Store (Local3, IRA2)
+		}
+		Return (BUFA)
+	}
+
+	Method (_SRS, 1, NotSerialized) {
+		CreateByteField (Arg0, 0x01, IRA1)
+		CreateByteField (Arg0, 0x02, IRA2)
+		ShiftLeft (IRA2, 0x08, Local0)
+		Or (Local0, IRA1, Local0)
+		Store (0x00, Local1)
+		ShiftRight (Local0, 0x01, Local0)
+		While (LGreater (Local0, 0x00)) {
+			Increment (Local1)
+			ShiftRight (Local0, 0x01, Local0)
+		}
+		Store(Local1,\_SB.PCI0.PMF.PIRC)
+	}
+}
+
+Device (LNKD) {
+	Name (_HID, EisaId ("PNP0C0F"))
+	Name (_UID, 0x04)
+	Method (_STA, 0, NotSerialized) {
+		If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled
+		Else                                    { Return (0x0B) } //Enabled
+	}
+	Method (_PRS, 0, Serialized) {
+		Name (BUFB, ResourceTemplate () {
+			IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+		})
+		Return (BUFB)
+	}
+	Method (_DIS, 0, NotSerialized) {
+		Store (0x00, \_SB.PCI0.PMF.PIRD )
+	}
+	Method (_CRS, 0, Serialized) {
+		Name (BUFB, ResourceTemplate () {
+			IRQ (Level, ActiveLow, Shared) {}
+		})
+		CreateByteField (BUFB, 0x01, IRA1)
+		CreateByteField (BUFB, 0x02, IRA2)
+		Store (0x00, Local2)
+		Store (0x00, Local3)
+		Store (\_SB.PCI0.PMF.PIRD, Local1)
+		If (LNot (LEqual (Local1, 0x00))) {  // Routing enable
+			If (LGreater (Local1, 0x07)) {
+				Subtract (Local1, 0x08, Local1)
+				ShiftLeft (One, Local1, Local3)
+			} Else {
+				If (LGreater (Local1, 0x00)) {
+					ShiftLeft (One, Local1, Local2)
+				}
+			}
+			Store (Local2, IRA1)
+			Store (Local3, IRA2)
+		}
+		Return (BUFB)
+	}
+	Method (_SRS, 1, NotSerialized) {
+		CreateByteField (Arg0, 0x01, IRA1)
+		CreateByteField (Arg0, 0x02, IRA2)
+		ShiftLeft (IRA2, 0x08, Local0)
+		Or (Local0, IRA1, Local0)
+		Store (0x00, Local1)
+		ShiftRight (Local0, 0x01, Local0)
+		While (LGreater (Local0, 0x00)) {
+			Increment (Local1)
+			ShiftRight (Local0, 0x01, Local0)
+		}
+		Store(Local1,\_SB.PCI0.PMF.PIRD)
+	}
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl
new file mode 100644
index 0000000000..54aae73aff
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2005 AMD
+ * Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
+ */
+
+Device (PG0A) {
+/* 8131 pcix bridge 1 */
+	Method (_ADR, 0, NotSerialized) {
+		Return (DADD(GHCD(HCIN, 0), 0x00000000))
+	}
+	Method (_PRW, 0, NotSerialized) {
+		//If (CondRefOf (\_S3, Local0)) {
+		//	Return (Package (0x02) { 0x29, 0x03 })
+		//} Else {
+			Return (Package (0x02) { 0x29, 0x01 })
+		//}
+	}
+	Name (APIC, Package (0x0c) {
+	// Slot 3 - PIRQ BCDA ---- verified
+		Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
+		Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+		Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+		Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+	// Slot 4 - PIRQ CDAB  ---- verified
+		Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
+		Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+		Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
+		Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
+	// Onboard NIC 1  - PIRQ DABC
+		Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
+		Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
+		Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
+		Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
+	// NIC 2	- PIRQ ABCD -- verified
+	//	Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
+	//	Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
+	//	Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
+	//	Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
+	// SERIAL ATA     - PIRQ BCDA
+	//	Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
+	//	Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
+	//	Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
+	//	Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
+	})
+	Name (PICM, Package (0x0c) {
+		Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
+		Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+	//	Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+	//	Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+	//	Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+	//	Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+	//	Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+	//	Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+	//	Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+	//	Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+	})
+	Method (_PRT, 0, NotSerialized) {
+		If (LNot (PICF)) { Return (PICM) }
+		Else             { Return (APIC) }
+	}
+}
+Device (PG0B) {
+/* 8131 pcix bridge 2 */
+	Method (_ADR, 0, NotSerialized) {
+		Return (DADD(GHCD(HCIN, 0), 0x00010000))
+	}
+	Method (_PRW, 0, NotSerialized) {
+		//If (CondRefOf (\_S3, Local0)) {
+		//	Return (Package (0x02) { 0x22, 0x03 })
+		//} Else {
+			Return (Package (0x02) { 0x22, 0x01 })
+		//}
+	}
+	Name (APIC, Package (0x04) {
+	// Slot A - PIRQ CDAB -- verfied
+		Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2
+		Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C },
+		Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D },
+		Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E }
+	})
+	Name (PICM, Package (0x04) {
+		Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
+		Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }
+	})
+	Method (_PRT, 0, NotSerialized) {
+		If (LNot (PICF)) { Return (PICM) }
+		Else             { Return (APIC) }
+	}
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl
new file mode 100644
index 0000000000..021ee1f279
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+#include "amd8111.asl" //real SB at first
+#include "amd8131.asl"