diff options
author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-03-27 16:06:34 +0200 |
---|---|---|
committer | Patrick Rudolph <siro@das-labor.org> | 2018-05-24 15:05:19 +0000 |
commit | 6308e0e92f624cb18a875ed04e41e1d15fc91054 (patch) | |
tree | acf117900e6cd9243cae5894b61264663a78cafd /src/mainboard/hp/compaq_8200_elite_sff/cmos.layout | |
parent | 21fa51475d86e5c68b5dd46233fb7889516def78 (diff) |
mb/hp: Add new port compaq_8200_elite_sff
Add new port based on autoport.
The board uses a NPCD378 SuperIO, that is full of custom hardware.
The 8MiB flash SOIC-8 can be accessed after cutting of a part of the
DIMM slot holder. The flash IC has no diode, powering a part of the
board while flashing externaly, including the Standby-LED.
The following have been tested and is working:
* Native raminit with up to four DIMMs
* Libgfxinit on DisplayPort
* USB
* EHCI debug
* Serial on RS232
* Ethernet
* PCIe on x4
* PCIe on x16
* SATA
* Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload
* Flashing internaly
* PS/2 is working
Untested:
* PCI slot
* LPT port
* VBIOS
* S3 resume
Not working:
* PSU fan managment (runs at 100%)
* Half of SuperIO functionality is unknown
TODO:
* Reverse engineer remaining SuperIO registers
* Reverse engineer SMM
Fixes on follow-up commits:
* Added PSU fan control
* Reverse engineered some of Super IO's HWM registers
* Added SMBIOS tables for IPMI
Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/hp/compaq_8200_elite_sff/cmos.layout')
-rw-r--r-- | src/mainboard/hp/compaq_8200_elite_sff/cmos.layout | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout new file mode 100644 index 0000000000..e90af85a09 --- /dev/null +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout @@ -0,0 +1,112 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 9 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 10 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 |