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authorAngel Pons <th3fanbus@gmail.com>2020-01-01 20:52:11 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 15:11:30 +0000
commita0a3eab36d04b6fa96b900493b1b1d0d2837c20a (patch)
tree036b36ec051a155032467c0bd6a86f84afa541b7 /src/mainboard/hp/2760p/devicetree.cb
parent0560a66450a600d8038933210dd3406cbb298131 (diff)
mb/hp/*/devicetree.cb: Inherit the subsystemid
Since all the `subsystemid` lines in these devicetrees use the same values, factor them out via inheritance. There are some exceptions though. There are some enabled devices which lack a `subsystemid` entry. Looks like HP uses the same subsystem ID on every device, so assume that these devices should also use that subsystem ID as well. While we are at it, tidy up all the now-empty device blocks. Change-Id: Iccd74fff9456e1204735a80ecc4f7685624cb78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38081 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/hp/2760p/devicetree.cb')
-rw-r--r--src/mainboard/hp/2760p/devicetree.cb89
1 files changed, 27 insertions, 62 deletions
diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb
index 06124ed30d..f33d0160b7 100644
--- a/src/mainboard/hp/2760p/devicetree.cb
+++ b/src/mainboard/hp/2760p/devicetree.cb
@@ -43,14 +43,11 @@ chip northbridge/intel/sandybridge
end
end
device domain 0x0 on
- device pci 00.0 on # Host bridge Host bridge
- subsystemid 0x103c 0x162a
- end
- device pci 01.0 off # PCIe Bridge for discrete graphics
- end
- device pci 02.0 on # Internal graphics VGA controller
- subsystemid 0x103c 0x162a
- end
+ subsystemid 0x103c 0x162a inherit
+
+ device pci 00.0 on end # Host bridge Host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
@@ -65,54 +62,27 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x21"
-
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0"
- device pci 16.0 on # Management Engine Interface 1
- subsystemid 0x103c 0x162a
- end
- device pci 16.1 off # Management Engine Interface 2
- end
- device pci 16.2 off # Management Engine IDE-R
- end
- device pci 16.3 off # Management Engine KT
- end
- device pci 19.0 on # Intel Gigabit Ethernet
- subsystemid 0x103c 0x162a
- end
- device pci 1a.0 on # USB2 EHCI #2
- subsystemid 0x103c 0x162a
- end
- device pci 1b.0 on # High Definition Audio Audio controller
- subsystemid 0x103c 0x162a
- end
- device pci 1c.0 on # PCIe Port #1
- subsystemid 0x103c 0x162a
- end
- device pci 1c.1 on # PCIe Port #2, ExpressCard
- subsystemid 0x103c 0x162a
- end
- device pci 1c.2 on # PCIe Port #3, SD/MMC
- subsystemid 0x103c 0x162a
- end
- device pci 1c.3 on # WLAN
- end
- device pci 1c.4 off # PCIe Port #5
- end
- device pci 1c.5 off # PCIe Port #6
- end
- device pci 1c.6 on # PCIe Port #7, WWAN
- end
- device pci 1c.7 off # PCIe Port #8
- end
- device pci 1d.0 on # USB2 EHCI #1
- subsystemid 0x103c 0x162a
- end
- device pci 1e.0 off # PCI bridge
- end
- device pci 1f.0 on # LPC bridge PCI-LPC bridge
- subsystemid 0x103c 0x162a
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2, ExpressCard
+ device pci 1c.2 on end # PCIe Port #3, SD/MMC
+ device pci 1c.3 on end # WLAN
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7, WWAN
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
@@ -121,15 +91,10 @@ chip northbridge/intel/sandybridge
device pnp ff.1 off end
end # kbc1126
end
- device pci 1f.2 on # SATA Controller 1
- subsystemid 0x103c 0x162a
- end
- device pci 1f.3 off # SMBus
- end
- device pci 1f.5 off # SATA Controller 2
- end
- device pci 1f.6 off # Thermal
- end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 off end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
end
end
end