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authorAngel Pons <th3fanbus@gmail.com>2020-01-01 20:56:08 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 17:26:16 +0000
commit942650f24009c08a73cb0b5f86dfa21fa1993fe4 (patch)
treecfac51b94055383d18c4f54b4e2dea6858ff355a /src/mainboard/hp/2570p
parent0e557aba4eae472addb13becb9467090d2d2b793 (diff)
mb/hp/*/devicetree.cb: Move northbridge devices up
It makes more sense for them to be above the southbridge block. Change-Id: I7dc06a46123f4bfc23d91f9c8cc4c9bdc4fb64f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/hp/2570p')
-rw-r--r--src/mainboard/hp/2570p/devicetree.cb8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb
index abac78752e..c659be68be 100644
--- a/src/mainboard/hp/2570p/devicetree.cb
+++ b/src/mainboard/hp/2570p/devicetree.cb
@@ -44,6 +44,11 @@ chip northbridge/intel/sandybridge
end
device domain 0x0 on
subsystemid 0x103c 0x17df inherit
+
+ device pci 00.0 on end # Host bridge Host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
@@ -95,8 +100,5 @@ chip northbridge/intel/sandybridge
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
- device pci 00.0 on end # Host bridge Host bridge
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics VGA controller
end
end