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authorDavid Milosevic <David.Milosevic@9elements.com>2024-08-19 14:59:40 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2024-09-27 11:35:23 +0000
commitb29b66c5f5935e0dfab18cca10b69101b75ce508 (patch)
treeef12bd2161cd9c165e22e2ddfaed61a3ed2560b9 /src/mainboard/hardkernel/odroid-h4/devicetree.cb
parent235c603a330b35418efd562990c7f37fa169f64c (diff)
mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+ board, but all of them use the same PCB (with different components). The four SATA ports on the mainboard are provided by an onboard ASMedia ASM1064B PCIe-to-SATA bridge. Unlike other mainboards in the tree using an ASMedia ASM1061 or ASM1062 PCIe-to-SATA bridge, the ODROID-H4+ comes with a SPI flash chip for the ASM1064B and does not seem to have issues regarding PCIe power management (e.g. ASPM) or unusable SATA AHCI mode. The ODROID-H4 comes with a single 16 MiB SPI flash chip. The ODROID-H4+ and the ODROID-H4 Ultra feature Dual BIOS, consisting of another 16 MiB SPI flash chip and a 3-pin header to select between them. The board can be flashed internally or using a SOIC-8 clip, but the M.2 slot may need to be empty for the clip to fit. Working: - DDR5 SO-DIMM slot - All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller - UART to emit spam - All video outputs (FSP GOP only lights up one output at a time) - All USB ports (on the Ethernet connectors and on EXT_HDR1) - M.2 M connector (PCIe only) - PCIe power management - Ethernet NICs - eMMC - HD audio codec and display audio - S3 suspend/resume - SeaBIOS <current version> - MrChromebox edk2 <current version> - Super I/O HWM on Linux (using out-of-tree it87 kernel module) - Booting Arch Linux from NVMe and SATA - Booting Windows 10 from NVMe Not working: - PECI: undocumented protocol and undocumented Super I/O - Resuming on Windows 10 BSODs with `VIDEO_TDR_FAILURE` Untested: - Fan curves: may need to lower the temperature limits a bit Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/hardkernel/odroid-h4/devicetree.cb')
-rw-r--r--src/mainboard/hardkernel/odroid-h4/devicetree.cb211
1 files changed, 211 insertions, 0 deletions
diff --git a/src/mainboard/hardkernel/odroid-h4/devicetree.cb b/src/mainboard/hardkernel/odroid-h4/devicetree.cb
new file mode 100644
index 0000000000..48f35fd421
--- /dev/null
+++ b/src/mainboard/hardkernel/odroid-h4/devicetree.cb
@@ -0,0 +1,211 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/alderlake
+ register "pmc_gpe0_dw0" = "PMC_GPP_A"
+ register "pmc_gpe0_dw1" = "PMC_GPP_R"
+ register "pmc_gpe0_dw2" = "PMC_GPD"
+
+ register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
+
+ register "enable_c6dram" = "true"
+
+ register "tcc_offset" = "10" # TCC of 90C
+
+ device domain 0 on
+ device ref igpu on
+ register "ddi_portA_config" = "1"
+ register "ddi_portB_config" = "1"
+ register "ddi_ports_config" = "{
+ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ }"
+ end
+ device ref xhci on
+ ## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1
+ ## pin header does not correlate with the numbering of the USB2 ports
+ ## on the ADL-N SoC. But schematics and lsusb agree with the mapping.
+ ##
+ ## For onboard USB Type-A ports, tune PHYs for short trace lengths as
+ ## the ODROID-H4 is a tiny board (and exact trace length is unknown).
+ ##
+ ## The USB2 ports on the EXT_HEAD1 pin header are meant to be cabled.
+ ## So, have these ports use medium trace length PHY settings instead.
+
+ register "usb2_ports" = "{
+
+#define ODROID_H4_USB2_PORT_REAR { \
+ .enable = 1, \
+ .ocpin = OC_SKIP, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_16P9MV, \
+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
+}
+
+ [0] = ODROID_H4_USB2_PORT_REAR, // USB3_LAN1 Bottom
+ [1] = ODROID_H4_USB2_PORT_REAR, // USB3_LAN1 Top
+ [2] = USB2_PORT_MID(OC_SKIP), // EXT_HEAD1 P7
+ [3] = USB2_PORT_MID(OC_SKIP), // EXT_HEAD1 P5
+ [4] = ODROID_H4_USB2_PORT_REAR, // USBLAN1 Top
+ [5] = USB2_PORT_MID(OC_SKIP), // EXT_HEAD1 P6
+ [6] = ODROID_H4_USB2_PORT_REAR, // USBLAN1 Bottom
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), // USB3_LAN1 Bottom
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), // USB3_LAN1 Top
+ }"
+
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A (Bottom Right)""
+ register "type" = "UPC_TYPE_USB3_A"
+ device ref usb2_port1 on end
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A (Top Right)""
+ register "type" = "UPC_TYPE_USB3_A"
+ device ref usb2_port2 on end
+ device ref usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 P7 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_PROPRIETARY"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 P5 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_PROPRIETARY"
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A (Top Left)""
+ register "type" = "UPC_TYPE_A"
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 P6 (EXT_HEAD1)""
+ register "type" = "UPC_TYPE_PROPRIETARY"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A (Bottom Left)""
+ register "type" = "UPC_TYPE_A"
+ device ref usb2_port7 on end
+ end
+ end
+ end
+ end
+ device ref i2c0 on
+ register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+ register "common_soc_config.i2c[0]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 80,
+ .fall_time_ns = 110,
+ }"
+ end
+ device ref i2c1 on
+ register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+ register "common_soc_config.i2c[1]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 80,
+ .fall_time_ns = 110,
+ }"
+ end
+ device ref emmc on
+ register "emmc_enable_hs400_mode" = "true"
+ end
+ device ref pcie_rp3 on # LAN1
+ register "pch_pcie_rp[PCH_RP(3)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp4 on # LAN2
+ register "pch_pcie_rp[PCH_RP(4)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp7 on # ASM1064B SATA
+ register "pch_pcie_rp[PCH_RP(7)]" = "{
+ .clk_src = 3,
+ .clk_req = 3, // Use hardwired CLKREQ# to allow clock gating
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end
+ device ref pcie_rp9 on # M.2 M (x4)
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 0,
+ .clk_req = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
+ }"
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+ "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
+ end
+ device ref pch_espi on
+ register "gen1_dec" = "0x00fc0201"
+ register "gen2_dec" = "0x007c0a01"
+ register "gen3_dec" = "0x000c03e1"
+ register "gen4_dec" = "0x001c02e1"
+
+ chip superio/ite/it8613e
+ register "ec.vin_mask" = "VIN0 | VIN1 | VIN2 | VIN4 | VIN5"
+ # TODO: figure out how to make PECI work
+ register "TMPIN1.mode" = "THERMAL_DIODE"
+ #register "TMPIN1.mode" = "THERMAL_PECI"
+ #register "TMPIN1.offset" = "0x56"
+ register "FAN2" = "{
+ .mode = FAN_SMART_AUTOMATIC,
+ .smart = {
+ .tmpin = 1,
+ .tmp_off = 20,
+ .tmp_start = 35,
+ .tmp_full = 70,
+ .tmp_delta = 1,
+ .pwm_start = 20,
+ .slope = 3,
+ .smoothing = 0,
+ },
+ }"
+
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ irq 0xf0 = 0x01
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa30
+ io 0x62 = 0xa20
+ irq 0x70 = 0x00
+ irq 0xf0 = 0x80
+ irq 0xfc = 0xa0
+ end
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0xa10
+ io 0x62 = 0xa00
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device ref hda on
+ register "pch_hda_dsp_enable" = "true"
+ register "pch_hda_sdi_enable[0]" = "true"
+ register "pch_hda_audio_link_hda_enable" = "true"
+ register "pch_hda_idisp_codec_enable" = "true"
+ register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+ register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+ end
+ device ref smbus on end
+
+ chip drivers/crb
+ device mmio 0xfed40000 on end
+ end
+ end
+end