diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-10-20 10:17:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-21 20:05:34 +0000 |
| commit | e2c6d9c7cb7973cd1177184ac36153e1667386a0 (patch) | |
| tree | 6bd85a6f0e433627ba4be58efa7764a69b5cea1d /src/mainboard/google | |
| parent | 48bd8577895bdd0ff86f22010a74e13ffa620425 (diff) | |
mb/google/brya/var/brask: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/gpio.c | 15 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc index 8fe978f6ef..d38141ca24 100644 --- a/src/mainboard/google/brya/variants/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/brask/Makefile.inc @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index 1f1d409f25..a23135bc90 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -10,6 +10,8 @@ static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -25,6 +27,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ @@ -59,8 +63,19 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |