diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-12-07 01:33:42 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-08 21:16:51 +0000 |
| commit | d49fafd531bb6ee3860da43ee0dc3bb81a135432 (patch) | |
| tree | fa2c239303fccb1be37a19d4471981e1d4c11cef /src/mainboard/google | |
| parent | 1e3b2ce061626e6c5a7d7f89d40a854bac16f3d4 (diff) | |
mb/*: Remove SATA mode config for CNL based mainboards
SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/google')
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 5826f79ba9..7d9d1e64ca 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake # FSP configuration register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 69e4e7d059..c975b9906c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -16,7 +16,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 021feba777..6a807a36b6 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -16,7 +16,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" |