diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-04-23 14:34:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:28:04 +0000 |
| commit | b1e8a8a6cee3e67962ecb03afd84aabb391ff9a8 (patch) | |
| tree | 4863dd592fce2e4f52ac8382407a4ee10e2e963c /src/mainboard/google | |
| parent | baecee105235f92556d7236ff5004f79e1a2249d (diff) | |
mb/google/brya: Enable GL9755 SD card reader
Enable GL9755 SD card reader.
BUG=b:185397257
TEST=SD card is functional in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/Kconfig.name | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/gpio.c | 6 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 8 |
4 files changed, 14 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5007836488..d53065f568 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -21,6 +21,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_ALDERLAKE + select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU if BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 39cda60d45..70af2d2c5c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -4,3 +4,4 @@ config BOARD_GOOGLE_BRYA0 select BASEBOARD_BRYA_LAPTOP select BOARD_ROMSIZE_KB_32768 select ADL_ENABLE_USB4_PCIE_RESOURCES + select DRIVERS_GENESYSLOGIC_GL9755 diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index b95ece1deb..5811b58dfc 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -154,7 +154,7 @@ static const struct pad_config gpio_table[] = { /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 0, DEEP), + PAD_CFG_GPO(GPP_D18, 1, DEEP), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), @@ -283,7 +283,7 @@ static const struct pad_config gpio_table[] = { /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_NC(GPP_H13, UP_20K), /* H14 : NC */ PAD_NC(GPP_H14, NONE), /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ @@ -394,6 +394,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_NC(GPP_H13, UP_20K), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index b115aeb6d7..a0e40b7ce3 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -12,6 +12,14 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" |