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authorJeremy Compostella <jeremy.compostella@intel.com>2022-12-02 11:07:09 -0700
committerJakub Czapiga <jacz@semihalf.com>2023-01-04 16:37:42 +0000
commit96d9b756690839c17b307a93b8a1898bd1c02ff5 (patch)
tree8c85b99313ab2c2825d0a190b823265dd66be00c /src/mainboard/google
parent9395cf9a2f867b5e5832fed3d0396962e4978e87 (diff)
mb/google/brya: Add romstage early graphics for brya
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/Makefile.inc1
-rw-r--r--src/mainboard/google/brya/gma-mainboard.ads13
-rw-r--r--src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb32
3 files changed, 45 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc
index c40f21c275..ab80e32d73 100644
--- a/src/mainboard/google/brya/Makefile.inc
+++ b/src/mainboard/google/brya/Makefile.inc
@@ -4,6 +4,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += romstage.c
+romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/google/brya/gma-mainboard.ads b/src/mainboard/google/brya/gma-mainboard.ads
new file mode 100644
index 0000000000..3b02f14d95
--- /dev/null
+++ b/src/mainboard/google/brya/gma-mainboard.ads
@@ -0,0 +1,13 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+ ports : constant Port_List :=
+ (eDP,
+ others => Disabled);
+end GMA.Mainboard;
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 70e7779545..efc2fcbc98 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -123,7 +123,37 @@ chip soc/intel/alderlake
}"
device domain 0 on
- device ref igpu on end
+ # The timing values can be derived from datasheet of display panel
+ # You can use EDID string to identify the type of display on the board
+ # use below command to get display info from EDID
+ # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
+
+ # refer to display PRM document (Volume 2b: Command Reference: Registers)
+ # for more info on display control registers
+ # https://01.org/linuxgraphics/documentation/hardware-specification-prms
+ #+-----------------------------+---------------------------------------+-----+
+ #| Intel docs | devicetree.cb | eDP |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power up delay | `gpu_panel_power_up_delay` | T3 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power Down delay | `gpu_panel_power_down_delay` | T10 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 |
+ #+-----------------------------+---------------------------------------+-----+
+ #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
+ #+-----------------------------+---------------------------------------+-----+
+ device ref igpu on
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
+ end
device ref dtt on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end