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authorAngel Pons <th3fanbus@gmail.com>2021-09-27 13:04:28 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-11-01 16:02:13 +0000
commit8d5b6747391919a8de05dd19308acc79f2b22659 (patch)
tree5a7149d7c0f8a53de9880daf20d93c5d2f5c7f3a /src/mainboard/google
parentfbca40c9cc127487e73a602bd2332bca866cdbdb (diff)
soc/intel/braswell: Set GNVS DPTE via devicetree
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/cyan/acpi_tables.c3
-rw-r--r--src/mainboard/google/cyan/devicetree.cb2
2 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c
index 42380d51b3..a8e030af87 100644
--- a/src/mainboard/google/cyan/acpi_tables.c
+++ b/src/mainboard/google/cyan/acpi_tables.c
@@ -15,9 +15,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* Enable DPTF */
- gnvs->dpte = 1;
-
/* Disable PMIC I2C port for ACPI for all boards except cyan */
struct device_nvs *dev_nvs = acpi_get_device_nvs();
if (!CONFIG(BOARD_GOOGLE_CYAN))
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index cec1682ed1..c968dfc0b7 100644
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -77,6 +77,8 @@ chip soc/intel/braswell
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
+ register "dptf_enable" = "true"
+
# Enable LPSS and LPE devices in ACPI mode
register "lpss_acpi_mode" = "1"
register "emmc_acpi_mode" = "0"