diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-09-18 19:53:08 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-20 19:25:13 +0000 |
| commit | 7d5452c42d01b62333ede92b0b6143c23af1c76d (patch) | |
| tree | 90bb49db2d9257f6b45d060b11fe86173651142d /src/mainboard/google | |
| parent | 5d982d72be849a15f98bb0583b25bbcd6eb7d315 (diff) | |
google/kahee: Fix number of memory channels
Kahlee has a single memory channel, not two. This corrects DMI type 17
reporting and the memory clear functions.
BUG=b:65403853, b:64193190
BRANCH=none
TEST=AGESA DMI reports the correct number of DIMMs.
Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/kahlee/OemCustomize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 2b3ac292f6..2043193f2e 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -21,7 +21,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |