diff options
| author | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-05-24 09:08:48 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-07-01 07:23:38 +0000 |
| commit | 7a294be356b44b5569682e652271f2aaddee91a3 (patch) | |
| tree | 5f21035da6556f576df690c027360446b86dde5e /src/mainboard/google | |
| parent | 5c02779ec80b47c902ec7c2abc5a0f6e61bb5c63 (diff) | |
mb/google/rex: Enable ACPI and add ACPI table
Enable ACPI configuration and add DSDT ACPI table.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rex/dsdt.asl | 20 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 1c9ed235c0..d848ac71f2 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_REX_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES config BOARD_GOOGLE_BASEBOARD_REX diff --git a/src/mainboard/google/rex/dsdt.asl b/src/mainboard/google/rex/dsdt.asl index 10d08e26e2..cecfe521fa 100644 --- a/src/mainboard/google/rex/dsdt.asl +++ b/src/mainboard/google/rex/dsdt.asl @@ -11,4 +11,24 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + /* Some generic macros */ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> } |