diff options
author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-09-09 18:43:22 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-03 08:26:28 +0000 |
commit | 74a06296608e4c868e101ea47c0a1389977ecd91 (patch) | |
tree | 1332211a34531c448be0d538d60bbfa5c0d57c41 /src/mainboard/google | |
parent | 73e6b8e3eb085110dad1d57e148ed78534b31fad (diff) |
mb/google/corsola: Add MediaTek MT8186 reference board
Add mainboard folder and drivers for new reference board 'Corsola'.
TEST=build pass
BUG=b:200134633
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/corsola/Kconfig | 25 | ||||
-rw-r--r-- | src/mainboard/google/corsola/Kconfig.name | 5 | ||||
-rw-r--r-- | src/mainboard/google/corsola/Makefile.inc | 16 | ||||
-rw-r--r-- | src/mainboard/google/corsola/board_info.txt | 6 | ||||
-rw-r--r-- | src/mainboard/google/corsola/bootblock.c | 8 | ||||
-rw-r--r-- | src/mainboard/google/corsola/chromeos.c | 15 | ||||
-rw-r--r-- | src/mainboard/google/corsola/chromeos.fmd | 45 | ||||
-rw-r--r-- | src/mainboard/google/corsola/devicetree.cb | 7 | ||||
-rw-r--r-- | src/mainboard/google/corsola/mainboard.c | 17 | ||||
-rw-r--r-- | src/mainboard/google/corsola/memlayout.ld | 3 | ||||
-rw-r--r-- | src/mainboard/google/corsola/reset.c | 7 | ||||
-rw-r--r-- | src/mainboard/google/corsola/romstage.c | 7 |
12 files changed, 161 insertions, 0 deletions
diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig new file mode 100644 index 0000000000..8b38d2bba4 --- /dev/null +++ b/src/mainboard/google/corsola/Kconfig @@ -0,0 +1,25 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_CORSOLA_COMMON + def_bool n + +if BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8186 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + +config MAINBOARD_DIR + string + default "google/corsola" + +config MAINBOARD_PART_NUMBER + string + default "Corsola" if BOARD_GOOGLE_CORSOLA +endif diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name new file mode 100644 index 0000000000..3b44019d0a --- /dev/null +++ b/src/mainboard/google/corsola/Kconfig.name @@ -0,0 +1,5 @@ +comment "Corsola" + +config BOARD_GOOGLE_CORSOLA + bool "-> Corsola" + select BOARD_GOOGLE_CORSOLA_COMMON diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc new file mode 100644 index 0000000000..4720dc586f --- /dev/null +++ b/src/mainboard/google/corsola/Makefile.inc @@ -0,0 +1,16 @@ +bootblock-y += memlayout.ld +bootblock-y += bootblock.c +bootblock-y += chromeos.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/board_info.txt b/src/mainboard/google/corsola/board_info.txt new file mode 100644 index 0000000000..3c37bdfd3f --- /dev/null +++ b/src/mainboard/google/corsola/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Corsola MediaTek MT8186 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c new file mode 100644 index 0000000000..99947c08b9 --- /dev/null +++ b/src/mainboard/google/corsola/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/mmio.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c new file mode 100644 index 0000000000..3f0937f693 --- /dev/null +++ b/src/mainboard/google/corsola/chromeos.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_recovery_mode_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 0; +} diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd new file mode 100644 index 0000000000..7194632e36 --- /dev/null +++ b/src/mainboard/google/corsola/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb new file mode 100644 index 0000000000..0c4bcb57c0 --- /dev/null +++ b/src/mainboard/google/corsola/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8186 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c new file mode 100644 index 0000000000..e6040fa7aa --- /dev/null +++ b/src/mainboard/google/corsola/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/corsola/memlayout.ld b/src/mainboard/google/corsola/memlayout.ld new file mode 100644 index 0000000000..0f1fcec9a0 --- /dev/null +++ b/src/mainboard/google/corsola/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/corsola/reset.c b/src/mainboard/google/corsola/reset.c new file mode 100644 index 0000000000..3a97ee5393 --- /dev/null +++ b/src/mainboard/google/corsola/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ +} diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c new file mode 100644 index 0000000000..891dc1b0d7 --- /dev/null +++ b/src/mainboard/google/corsola/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> + +void platform_romstage_main(void) +{ +} |