diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-19 15:38:36 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-10-21 19:01:29 +0000 |
| commit | 72cc0467d7ca1036787011027fc4848772b3bca0 (patch) | |
| tree | 7063e6b1f474b55a81a40e521ecbd7cc3ba356c3 /src/mainboard/google | |
| parent | 0bf9afed7f7f1cbcc42bfd5c98d40ba094cb8478 (diff) | |
mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO Descriptor
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be
de-asserted before PCIe link training during S0i3 resume. Otherwise the
concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume.
This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so
that SMU de-asserts this reset on S0i3 resume.
BUG=b:199780346
TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for
500 iterations. Ensure that the PCIe devices enumerate fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/guybrush/port_descriptors.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 177b538e64..abb854e44c 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -135,6 +135,9 @@ void mainboard_get_dxio_ddi_descriptors( if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; + if (variant_has_pcie_wwan()) + guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; + *dxio_descs = guybrush_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); |