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authorMatt Papageorge <matthewpapa07@gmail.com>2020-07-30 15:32:34 -0500
committerFurquan Shaikh <furquan@google.com>2020-08-28 17:54:19 +0000
commit48b2b2b8c14a6dcc79a4cb2974ef90370586e1a4 (patch)
treecef610c5cab03a4cac8698acf1eaa4fb1f8b6fb0 /src/mainboard/google
parentb87effe1dde3cc3f81a6afef073009ba808e11a7 (diff)
mb/google/zork: Disable SATA device for all Zork platforms to save power
SATA is currently turned on in the Dalboz and Trembyle base board variant devicetrees, even though no Google/Zork device uses SATA; for mass storage they either use eMMC or NVME PCIe SSDs. This patch disables both the SATA PCIe device and the bus where it was the only enabled device on. The next patch in this patch train sets a new FSP-M UPD setting BUG=b:162302027 Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068 Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb4
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 5a86b1cb5d..c7616020ff 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -286,8 +286,8 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
- device pci 8.2 on # Internal GPP Bridge 0 to Bus B
- device pci 0.0 on end # AHCI
+ device pci 8.2 off # Internal GPP Bridge 0 to Bus B
+ device pci 0.0 off end # AHCI
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 62395a163e..4413857cbb 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -315,8 +315,8 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
- device pci 8.2 on # Internal GPP Bridge 0 to Bus B
- device pci 0.0 on end # AHCI
+ device pci 8.2 off # Internal GPP Bridge 0 to Bus B
+ device pci 0.0 off end # AHCI
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge