diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-08 20:47:11 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:38 +0000 |
| commit | 45b6080561748fe579c8ee901811cf4043383c2f (patch) | |
| tree | b9f37ad3e3962571401fafa2578788f0feb27d5a /src/mainboard/google | |
| parent | 9f0285b6fe46d6ec76faad0c099239c227e5caa1 (diff) | |
soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
3 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 067222440c..f5dc01910d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -50,6 +50,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[2]" = "8" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[8]" = "1" # Mark unused SRCCLKREQs as so register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a93a38a830..1fa7d2fa5f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -120,11 +120,13 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" + register "PcieRpSlotImplemented[10]" = "1" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" @@ -138,6 +140,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 8fdc0674db..808127f86d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -15,6 +15,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 register "PcieRpEnable[7]" = "0" |