google/glados: add new board

Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10997
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

28 files changed, 1796 insertions, 0 deletions

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
new file mode 100644
index 0000000000..c7df2a388b
--- /dev/null
+++ b/src/mainboard/google/glados/Kconfig
@@ -0,0 +1,52 @@
+if BOARD_GOOGLE_GLADOS
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select CACHE_ROM
+	select CHROMEOS
+	select CHROMEOS_RAMOOPS_DYNAMIC
+	select CHROMEOS_VBNV_CMOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_LPC
+	select EC_GOOGLE_CHROMEEC_MEC
+	select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
+	select EC_SOFTWARE_SYNC
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_SMI_HANDLER
+	select LID_SWITCH
+	select MAINBOARD_HAS_CHROMEOS
+	select MARK_GRAPHICS_MEM_WRCOMB
+	select MMCONF_SUPPORT
+	select MONOTONIC_TIMER_MSR
+	select SOC_INTEL_SKYLAKE
+	select VBOOT_OPROM_MATTERS
+	select VIRTUAL_DEV_SWITCH
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config BOOT_MEDIA_SPI_BUS
+	int
+	default 0
+
+config MAINBOARD_DIR
+	string
+	default "google/glados"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Glados"
+
+config MAX_CPUS
+	int
+	default 8
+
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x3
+
+endif
diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name
new file mode 100644
index 0000000000..3d1bd68460
--- /dev/null
+++ b/src/mainboard/google/glados/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_GLADOS
+	bool "Glados"
diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc
new file mode 100644
index 0000000000..93fc3d6430
--- /dev/null
+++ b/src/mainboard/google/glados/Makefile.inc
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+subdirs-y += spd
+
+romstage-y += pei_data.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+
+ramstage-y += mainboard.c
+ramstage-y += pei_data.c
+ramstage-y += ramstage.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled
new file mode 100644
index 0000000000..7d1725ac44
--- /dev/null
+++ b/src/mainboard/google/glados/abuild.disabled
@@ -0,0 +1,2 @@
+Successful builds for this board require the Skylake FSP binary and header files
+along with the Skylake microcode files from Intel.
diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl
new file mode 100644
index 0000000000..2d8146cf51
--- /dev/null
+++ b/src/mainboard/google/glados/acpi/chromeos.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Name (OIPG, Package() {
+	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button
+	Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect
+})
diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl
new file mode 100644
index 0000000000..8e7532de34
--- /dev/null
+++ b/src/mainboard/google/glados/acpi/ec.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/glados/ec.h>
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
new file mode 100644
index 0000000000..ab40d62456
--- /dev/null
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define BOARD_TRACKPAD_I2C_ADDR		0x15
+#define BOARD_TRACKPAD_IRQ		0x33
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+
+	/* Keyboard Backlight interface via EC */
+	Device (KBLT) {
+		Name (_HID, "GOOG0002")
+		Name (_UID, 1)
+
+		/* Read current backlight value */
+		Method (KBQC, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.KBLV)
+		}
+
+		/* Write new backlight value */
+		Method (KBCM, 1)
+		{
+			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
+		}
+	}
+}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+/* Trackpad */
+Scope (\_SB.PCI0.I2C1)
+{
+	Device (ELAN)
+	{
+		Name (_HID, "ELAN0000")
+		Name (_DDN, "Elan Touchpad")
+		Name (_UID, 3)
+		Name (_S0W, 4)
+		Name (ISTP, 1) /* TouchPad */
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TRACKPAD_I2C_ADDR,	/* SlaveAddress */
+				ControllerInitiated,		/* SlaveMode */
+				400000,				/* ConnectionSpeed */
+				AddressingMode7Bit,		/* AddressingMode */
+				"\\_SB.PCI0.I2C1",		/* ResourceSource */
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_TRACKPAD_IRQ
+			}
+		})
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
diff --git a/src/mainboard/google/glados/acpi/superio.asl b/src/mainboard/google/glados/acpi/superio.asl
new file mode 100644
index 0000000000..932fef7430
--- /dev/null
+++ b/src/mainboard/google/glados/acpi/superio.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/glados/ec.h>
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/glados/acpi_tables.c b/src/mainboard/google/glados/acpi_tables.c
new file mode 100644
index 0000000000..cb0afc485b
--- /dev/null
+++ b/src/mainboard/google/glados/acpi_tables.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include "thermal.h"
+
+extern const unsigned char AmlCode[];
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* Disable USB ports in S5 */
+	gnvs->s5u0 = 0;
+
+	gnvs->tmps = TEMPERATURE_SENSOR_ID;
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	return acpi_madt_irq_overrides(current);
+}
diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c
new file mode 100644
index 0000000000..f1ff43b16c
--- /dev/null
+++ b/src/mainboard/google/glados/chromeos.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <rules.h>
+#include <soc/gpio.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#if ENV_RAMSTAGE
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT	6
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio *gpio;
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	gpio = gpios->gpios;
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
+		     get_recovery_mode_switch());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
+		     get_developer_mode_switch());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid",
+		     get_lid_switch());
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+	fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
+}
+#endif /* ENV_RAMSTAGE */
+
+int get_lid_switch(void)
+{
+	return 1;
+}
+/* The dev-switch is virtual */
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout
new file mode 100644
index 0000000000..20afaf74d6
--- /dev/null
+++ b/src/mainboard/google/glados/cmos.layout
@@ -0,0 +1,140 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2015 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
new file mode 100644
index 0000000000..206086667b
--- /dev/null
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -0,0 +1,108 @@
+chip soc/intel/skylake
+
+	# Enable deep Sx states
+	register "deep_s3_enable" = "1"
+	register "deep_s5_enable" = "1"
+
+	# Must leave UART0 enabled or SD/eMMC will not work as PCI
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart0] = PchSerialIoPci, \
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
+	}"
+
+	# Enable Root port 1 and 5.
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	# Enable CLKREQ#
+	register "PcieRpClkReqSupport[0]" = "1"
+	register "PcieRpClkReqSupport[4]" = "1"
+	# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+	register "PcieRpClkReqNumber[0]" = "1"
+	register "PcieRpClkReqNumber[4]" = "2"
+
+	register "ScsEmmcEnabled" = "1"
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsSdCardEnabled" = "1"
+	register "EnableAzalia" = "1"
+	register "DspEnable" = "1"
+	register "IoBufferOwnership" = "3"
+
+	register "ProbelessTrace" = "0"
+	register "EnableTraceHub" = "0"
+	register "EnableLan" = "0"
+	register "EnableSata" = "0"
+	register "IshEnable" = "0"
+	register "XdciEnable" = "0"
+	register "SsicPortEnable" = "0"
+	register "SmbusEnable" = "0"
+	register "Cio2Enable" = "0"
+	register "PttSwitch" = "0"
+	register "SkipExtGfxScan" = "1"
+
+	# Embedded Controller host command window
+	register "gen1_dec" = "0x00fc0801"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 14.0 on  end # USB 3.0 xHCI Controller
+		device pci 14.1 off end # USB Device Controller (OTG)
+		device pci 14.2 on  end # Thermal Subsystem
+		device pci 15.0 on  end # I2C Controller #0
+		device pci 15.1 on  end # I2C Controller #1
+		device pci 15.2 off end # I2C Controller #2
+		device pci 15.3 off end # I2C Controller #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Intel MEI #3
+		device pci 17.0 on  end # SATA Controller
+		device pci 19.0 on  end # UART Controller #2
+		device pci 19.1 off end # I2C Controller #5
+		device pci 19.2 on  end # I2C Controller #4
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 off end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1e.4 on  end # eMMC
+		device pci 1e.6 on  end # SDCard
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC Interface
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel High Definition Audio
+		device pci 1f.4 off end # SMBus Controller
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE Controller
+	end
+end
diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl
new file mode 100644
index 0000000000..6ac0be425a
--- /dev/null
+++ b/src/mainboard/google/glados/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/skylake/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/skylake/acpi/globalnvs.asl>
+
+	// CPU
+	#include <soc/intel/skylake/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/skylake/acpi/systemagent.asl>
+			#include <soc/intel/skylake/acpi/pch.asl>
+		}
+	}
+
+	// Chrome OS specific
+	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	// Chipset specific sleep states
+	#include <soc/intel/skylake/acpi/sleepstates.asl>
+
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c
new file mode 100644
index 0000000000..c491ad5787
--- /dev/null
+++ b/src/mainboard/google/glados/ec.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+	printk(BIOS_DEBUG, "mainboard_ec_init\n");
+	post_code(0xf0);
+
+	/* Restore SCI event mask on resume. */
+	if (acpi_slp_type == 3) {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S3_WAKE_EVENTS);
+
+		/* Disable SMI and wake events */
+		google_chromeec_set_smi_mask(0);
+
+		/* Clear pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+		/*
+		 * Set SCI mask.OS may not generate SMI event to set
+		 * this on S3 resume.
+		 */
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+	} else {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S5_WAKE_EVENTS);
+	}
+
+	/* Clear wake event mask */
+	google_chromeec_set_wake_mask(0);
+	post_code(0xf1);
+}
diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h
new file mode 100644
index 0000000000..9da9d9f0b2
--- /dev/null
+++ b/src/mainboard/google/glados/ec.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPP_E16 is EC_SCI_L */
+#define EC_SCI_GPI   16 /* TODO: Update this */
+/* GPP_E15 is EC_SMI_L */
+#define EC_SMI_GPI   15 /* TODO: Update this */
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/glados/fadt.c b/src/mainboard/google/glados/fadt.c
new file mode 100644
index 0000000000..7948f938d0
--- /dev/null
+++ b/src/mainboard/google/glados/fadt.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 5;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	acpi_fill_in_fadt(fadt);
+
+	header->checksum = acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
new file mode 100644
index 0000000000..35b1ae46ea
--- /dev/null
+++ b/src/mainboard/google/glados/gpio.h
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+const GPIO_INIT_CONFIG mainboard_gpio_table[] = {
+/* RCIN# */
+{GPIO_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* LAD0 */
+{GPIO_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* LAD1 */
+{GPIO_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioTermNone}},
+/* LAD2 */
+{GPIO_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* LAD3 */
+{GPIO_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* LFRAME# */
+{GPIO_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SERIRQ */
+{GPIO_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* CLKRUN# */
+{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* CLKOUT_LPC0 */
+{GPIO_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SUSWARN# tied to SUSACK# */
+{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SUS_STAT# TP27 */
+{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SUSACK# tied to SUSWARN# */
+{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_1P8_SEL */
+{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_PWR_EN# */
+{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* TRACKPAD_INT_L */
+{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep,
+	GpioTermNone}},
+/* SRCCLKREQ1# / WLAN_PCIE_CLKREQ_L */
+{GPIO_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* SRCCLKREQ2# / KEPLER_PCIE_CLKREQ_L */
+{GPIO_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* EXT_PWR_GATE# */
+{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* SLP_S0# */
+{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* PLTRST# */
+{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* WLAN_PCIE_WAKE_L */
+{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* SMBCLK (XDP) */
+{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SMBDATA (XDP) */
+{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EC_IN_RW */
+{GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* EN_PP3300_KEPLER */
+{GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
+/* PCH_MEM_CONFIG[0] */
+{GPIO_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* PCH_MEM_CONFIG[1] */
+{GPIO_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* PCH_MEM_CONFIG[2] */
+{GPIO_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* PCH_MEM_CONFIG[3] */
+{GPIO_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2C0_SDA */
+{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2C0_SCL */
+{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2C1 SDA */
+{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2C1 SDA */
+{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* UART2_RXD */
+{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* UART2_TXD */
+{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EN_PP3300_DX_TOUCHSCREEN */
+{GPIO_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
+/* PCH_WP */
+{GPIO_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}},
+/* EN_PP3300_DX_EMMC */
+{GPIO_LP_GPP_D5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EN_PP1800_DX_EMMC */
+{GPIO_LP_GPP_D6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* USBA_1_ILIM_SEL_L */
+{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* USBA_2_ILIM_SEL_L */
+{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EN_PP3300_DX_CAM */
+{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* DMIC_CLK1 */
+{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* DMIC_DATA1 */
+{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* DMIC_CLK0 */
+{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* DMIC_DATA0 */
+{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2S_MCLK */
+{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* TPM_PIRQ_L */
+{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* TOUCHSCREEN_INT_L */
+{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep,
+	GpioTermNone}},
+/* USB2_OC0# */
+{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* USB2_OC1# */
+{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* USB2_OC2# */
+{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* USB2_OC3# */
+{GPIO_LP_GPP_E12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* DDPB_HPD0 */
+{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* DDPC_HPD1 */
+{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* EC_SMI_L */
+{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* EC_SCI_L */
+{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* EDP_HPD */
+{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/*
+ * The next 4 pads are for bit banging the amplifiers. They are connected
+ * together with i2s0 signals. For default behavior of i2s make these
+ * gpio inupts.
+ */
+/* I2S2_SCLK */
+{GPIO_LP_GPP_F0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2S2_SFRM */
+{GPIO_LP_GPP_F1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2S2_TXD */
+{GPIO_LP_GPP_F2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2S2_RXD */
+{GPIO_LP_GPP_F3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2C4_SDA */
+{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* I2C4_SCL */
+{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* MIC_INT_L */
+{GPIO_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,
+	GpioOutDefault, (GpioIntApic | GpioIntEdge), GpioResetDeep,
+	GpioTermNone}},
+/* EMMC_CMD */
+{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA0 */
+{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA1 */
+{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA2 */
+{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA3 */
+{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA4 */
+{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA5 */
+{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA6 */
+{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_DATA7 */
+{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_RCLK */
+{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_CLK */
+{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* EMMC_CMD */
+{GPIO_LP_GPP_F23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_CMD */
+{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_DATA0 */
+{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_DATA1 */
+{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_DATA2 */
+{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_DATA3 */
+{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_CD# */
+{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SD_CLK# */
+{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* SD_WP# */
+{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* ACPRESENT# */
+{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* EC_PCH_WAKE_L */
+{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
+/* PWRBTN# */
+{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
+	GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
+/* SLP_S3# */
+{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SLP_S4# */
+{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SUSCLK */
+{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
+/* SLP_S5# */
+{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
+	GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
+{END_OF_GPIO_TABLE,  {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,
+	GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
+};
+
+#endif
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
new file mode 100644
index 0000000000..26b622ab1e
--- /dev/null
+++ b/src/mainboard/google/glados/mainboard.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <device/device.h>
+#include "ec.h"
+
+static void mainboard_init(device_t dev)
+{
+	if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC))
+		mainboard_ec_init();
+}
+
+/*
+ * mainboard_enable is executed as first thing after
+ * enumerate_buses().
+ */
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c
new file mode 100644
index 0000000000..677ea32d0a
--- /dev/null
+++ b/src/mainboard/google/glados/pei_data.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	/* DQ byte map */
+	const u8 dq_map[2][12] = {
+		  {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
+		   0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
+		  {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC ,
+		   0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
+	/* DQS CPU<>DRAM map */
+	const u8 dqs_map[2][8] = {
+		{0, 1, 3, 2, 4, 5, 6, 7},
+		{1, 0, 4, 5, 2, 3, 6, 7} };
+
+	/* Rcomp resistor*/
+	const u16 RcompResistor[3] = {200, 81, 162 };
+
+	/* Rcomp target*/
+	const u16 RcompTarget[5]   = {100, 40, 40, 23, 40};
+
+	pei_data->ec_present = 1;
+	/* One installed DIMM per channel */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+	memcpy(pei_data->RcompResistor, RcompResistor,
+		 sizeof(RcompResistor));
+	memcpy(pei_data->RcompTarget, RcompTarget,
+		 sizeof(RcompTarget));
+}
diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c
new file mode 100644
index 0000000000..f31511e8bc
--- /dev/null
+++ b/src/mainboard/google/glados/ramstage.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+{
+	params->GpioTablePtr = (UINT32 *)mainboard_gpio_table;
+}
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
new file mode 100644
index 0000000000..afcad8cad7
--- /dev/null
+++ b/src/mainboard/google/glados/romstage.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include "spd/spd.h"
+
+void mainboard_romstage_entry(struct romstage_params *params)
+{
+	/* Fill out PEI DATA */
+	mainboard_fill_pei_data(params->pei_data);
+	mainboard_fill_spd_data(params->pei_data);
+	/* Initliaze memory */
+	romstage_common(params);
+}
+
+void mainboard_memory_init_params(struct romstage_params *params,
+				  MEMORY_INIT_UPD *memory_params)
+{
+	if (params->pei_data->spd_data[0][0][0] != 0) {
+		memory_params->MemorySpdPtr00 =
+				(UINT32)(params->pei_data->spd_data[0][0]);
+		memory_params->MemorySpdPtr10 =
+				(UINT32)(params->pei_data->spd_data[1][0]);
+		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
+				memory_params->MemorySpdPtr00);
+		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
+				memory_params->MemorySpdPtr01);
+		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
+				memory_params->MemorySpdPtr10);
+		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
+				memory_params->MemorySpdPtr11);
+	}
+	memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
+			sizeof(params->pei_data->dq_map[0]));
+	memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
+			sizeof(params->pei_data->dq_map[1]));
+	memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
+			sizeof(params->pei_data->dqs_map[0]));
+	memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
+			sizeof(params->pei_data->dqs_map[1]));
+	memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
+			sizeof(params->pei_data->RcompResistor));
+	memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
+			sizeof(params->pei_data->RcompTarget));
+	memory_params->MemorySpdDataLen = SPD_LEN;
+	memory_params->DqPinsInterleaved = FALSE;
+}
diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c
new file mode 100644
index 0000000000..164bd8e465
--- /dev/null
+++ b/src/mainboard/google/glados/smihandler.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+#include "ec.h"
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		smm_get_gnvs()->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+	u8 cmd = 0;
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	u32 pm1_cnt;
+	cmd = google_chromeec_get_event();
+
+	/* Log this event */
+	if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd)
+		elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+
+	switch (cmd) {
+	case EC_HOST_EVENT_LID_CLOSED:
+		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+		/* Go to S5 */
+		pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+		pm1_cnt |= (0xf << 10);
+		outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+		break;
+	}
+#endif
+	return cmd;
+}
+
+/* gpi_sts is GPIO 47:32 */
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+	if (gpi_sts & (1 << EC_SMI_GPI)) {
+		/* Process all pending events */
+		while (mainboard_smi_ec() != 0)
+			;
+	}
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	/* Disable USB charging if required */
+	switch (slp_typ) {
+	case 3:
+		if (smm_get_gnvs()->s3u0 == 0) {
+			google_chromeec_set_usb_charge_mode(
+				0, USB_CHARGE_MODE_DISABLED);
+			google_chromeec_set_usb_charge_mode(
+				1, USB_CHARGE_MODE_DISABLED);
+		}
+
+		/* Enable wake events */
+		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+		break;
+	case 5:
+		if (smm_get_gnvs()->s5u0 == 0) {
+			google_chromeec_set_usb_charge_mode(
+				0, USB_CHARGE_MODE_DISABLED);
+			google_chromeec_set_usb_charge_mode(
+				1, USB_CHARGE_MODE_DISABLED);
+		}
+
+		/* Enable wake events */
+		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+		break;
+	}
+
+	/* Disable SCI and SMI events */
+	google_chromeec_set_smi_mask(0);
+	google_chromeec_set_sci_mask(0);
+
+	/* Clear pending events that may trigger immediate wake */
+	while (google_chromeec_get_event() != 0)
+		;
+#endif
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	switch (apmc) {
+	case APM_CNT_ACPI_ENABLE:
+		google_chromeec_set_smi_mask(0);
+		/* Clear all pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+		break;
+	case APM_CNT_ACPI_DISABLE:
+		google_chromeec_set_sci_mask(0);
+		/* Clear all pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+		break;
+	}
+#endif
+	return 0;
+}
diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc
new file mode 100644
index 0000000000..d8c0c51109
--- /dev/null
+++ b/src/mainboard/google/glados/spd/Makefile.inc
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+## Copyright (C) 2015 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# SPD data by index.  No method for board identification yet
+SPD_SOURCES = samsung_dimm_K4E6E304EE-EGCF	# 0
+SPD_SOURCES += empty	# 1
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/glados/spd/empty.spd.hex b/src/mainboard/google/glados/spd/empty.spd.hex
new file mode 100644
index 0000000000..9ec39f1ba4
--- /dev/null
+++ b/src/mainboard/google/glados/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex
new file mode 100644
index 0000000000..41ee49ac38
--- /dev/null
+++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
new file mode 100644
index 0000000000..5ee12f5f57
--- /dev/null
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include "spd.h"
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+	const int spd_banks[8] = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	const int spd_capmb[8] = {  1,  2,  4,  8, 16, 32, 64,  0 };
+	const int spd_rows[8]  = { 12, 13, 14, 15, 16, -1, -1, -1 };
+	const int spd_cols[8]  = {  9, 10, 11, 12, -1, -1, -1, -1 };
+	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
+	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
+	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	char spd_name[SPD_PART_LEN+1] = { 0 };
+
+	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+	int rows  = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+	int cols  = spd_cols[spd[SPD_ADDRESSING] & 7];
+	int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+	int devw  = spd_devw[spd[SPD_ORGANIZATION] & 7];
+	int busw  = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+	/* Module type */
+	printk(BIOS_INFO, "SPD: module type is ");
+	switch (spd[SPD_DRAM_TYPE]) {
+	case SPD_DRAM_DDR3:
+		printk(BIOS_INFO, "DDR3\n");
+		break;
+	case SPD_DRAM_LPDDR3:
+		printk(BIOS_INFO, "LPDDR3\n");
+		break;
+	default:
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		break;
+	}
+
+	/* Module Part Number */
+	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+	spd_name[SPD_PART_LEN] = 0;
+	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+	printk(BIOS_INFO,
+		"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
+		banks, ranks, rows, cols, capmb);
+	printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+		devw, busw);
+
+	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+		printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+		       capmb / 8 * busw / devw * ranks);
+	}
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+	char *spd_file;
+	size_t spd_file_len;
+	int spd_index;
+
+	/* Load SPD data from CBFS */
+	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+		&spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	/* make sure we have at least one SPD in the file. */
+	if (spd_file_len < SPD_LEN)
+		die("Missing SPD data.");
+
+	/* Add board SKU detection here.  Currently we only support one. */
+	spd_index = 0;
+
+	/* Make sure we did not overrun the buffer */
+	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+		spd_index = 0;
+	}
+
+	/* Assume same memory in both channels */
+	spd_index *= SPD_LEN;
+	memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
+	memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
+
+	/* Make sure a valid SPD was found */
+	if (pei_data->spd_data[0][0][0] == 0)
+		die("Invalid SPD data.");
+
+	mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h
new file mode 100644
index 0000000000..abb964ed82
--- /dev/null
+++ b/src/mainboard/google/glados/spd/spd.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN			256
+
+#define SPD_DRAM_TYPE		2
+#define  SPD_DRAM_DDR3		0x0b
+#define  SPD_DRAM_LPDDR3	0xf1
+#define SPD_DENSITY_BANKS	4
+#define SPD_ADDRESSING		5
+#define SPD_ORGANIZATION	7
+#define SPD_BUS_DEV_WIDTH	8
+#define SPD_PART_OFF		128
+#define  SPD_PART_LEN		18
+
+#endif
diff --git a/src/mainboard/google/glados/thermal.h b/src/mainboard/google/glados/thermal.h
new file mode 100644
index 0000000000..ef03d71713
--- /dev/null
+++ b/src/mainboard/google/glados/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MAINBOARD_THERMAL_H_
+#define _MAINBOARD_THERMAL_H_
+
+#define TEMPERATURE_SENSOR_ID		0	/* PECI */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		99
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE			100
+
+#endif /* _MAINBOARD_THERMAL_H_ */