diff options
| author | Leo Chou <leo.chou@lcfc.corp-partner.google.com> | 2022-11-16 10:07:23 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-17 13:29:18 +0000 |
| commit | 3e8f8c162d61dc6dbe982a9d6906ab925418e96e (patch) | |
| tree | f8a01102b78e84c4490a575cbf0ee3ff82377d1d /src/mainboard/google | |
| parent | 51c311827e5f83e0d62ac03938ca50159aa6aee7 (diff) | |
mb/google/nissa/var/pujjo: Tune timing on SD device RTD3
Tune timing between power on and reset on SD device RTD3.
BUG=b:250746988
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I1ea77ec8381000249229653f1c0b9044bdf7866d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 0a5624cada..4bc96f9b43 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -543,6 +543,7 @@ chip soc/intel/alderlake register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" register "srcclk_pin" = "3" + register "enable_delay_ms" = "50" device generic 0 on end end probe SD_CARD SD_PRESENT |