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authorYidi Lin <yidilin@chromium.org>2024-04-19 12:04:01 +0800
committerYu-Ping Wu <yupingso@google.com>2024-11-13 02:48:07 +0000
commit35cfefd1a468565c7321badd8a23ca21fed88d20 (patch)
treeb28cbfafcccb869e86bb863b27197fe1cfb3c112 /src/mainboard/google
parenta7ed63cbc8e2f2f9bd874a35653e8da213ad6151 (diff)
mb/google/rauru: Pass reset gpio parameter to BL31
Pass the reset gpio parameter to BL31 to support SoC reset. BUG=b:334753311 TEST=run reboot command Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84933 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/rauru/mainboard.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c
index a2d725a79f..c2d24e1228 100644
--- a/src/mainboard/google/rauru/mainboard.c
+++ b/src/mainboard/google/rauru/mainboard.c
@@ -2,6 +2,7 @@
#include <device/device.h>
#include <gpio.h>
+#include <soc/bl31.h>
#include <soc/pcie.h>
#include <soc/usb.h>
@@ -23,6 +24,9 @@ static void mainboard_init(struct device *dev)
{
setup_usb_host();
power_on_fpmcu();
+
+ if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
+ register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);
}
static void mainboard_enable(struct device *dev)