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authorVidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>2022-05-18 18:38:38 +0530
committerPaul Fagerburg <pfagerburg@chromium.org>2022-06-03 15:27:07 +0000
commit295a7508b8cd66b2934ed9b5ca253f683775150f (patch)
treef66022c133aa38c01e7fead1541b4826715b73e0 /src/mainboard/google
parent89818d1da7406bd9571d7d7ac4c3a5629b9bb368 (diff)
mb/google/brya/variants/nereid: Add DPTF passive and critical policies for Nereid
BUG=b:233030505 BRANCH=None TEST=Build FW and test on Nereid board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: I195f4b507ee57948751f0119735d8350dfce984b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/variants/nereid/overridetree.cb52
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb
index e2b82383db..c377e5b83c 100644
--- a/src/mainboard/google/brya/variants/nereid/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb
@@ -35,6 +35,58 @@ chip soc/intel/alderlake
}"
device domain 0 on
+ device ref dtt on
+ chip drivers/intel/dptf
+ ## sensor information
+ register "options.tsr[0].desc" = ""Memory""
+ register "options.tsr[1].desc" = ""Charger""
+ register "options.tsr[2].desc" = ""Ambient""
+
+ # TODO: below values are initial reference values only
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
+ [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
+ }"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+ }"
+
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 3000,
+ .max_power = 6000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200
+ },
+ .pl2 = {
+ .min_power = 25000,
+ .max_power = 25000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000
+ }
+ }"
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 1700 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+
+ device generic 0 on end
+ end
+ end
device ref i2c1 on
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""