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authorEren Peng <peng.eren@inventec.corp-partner.google.com>2024-04-25 13:25:05 +0800
committerMartin L Roth <gaumless@gmail.com>2024-05-12 18:51:46 +0000
commit1a395728dfdb6a32757ba7e120eb0e62d503e447 (patch)
treef8fab5fcc83fd08b4b007b242677fb68b3cba191 /src/mainboard/google
parenta56baa1d50f7bbc7533a396b6c2e236109a14a47 (diff)
mb/google/brox/var/greenbayupoc: Configure board for SODIMM use
Configure SODIMM settings for greenbayupoc. The SODIMM settings are copied from mainboard/google/brya/variants/baseboard/brask/memory.c. BUG=b:336955026, b:332230842 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM. Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brox/Kconfig3
-rw-r--r--src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk3
-rw-r--r--src/mainboard/google/brox/variants/greenbayupoc/memory.c42
-rw-r--r--src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk5
-rw-r--r--src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt6
-rw-r--r--src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt11
-rw-r--r--src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb1
7 files changed, 48 insertions, 23 deletions
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index efe10d28a2..908612d68b 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -44,7 +44,7 @@ config BOARD_GOOGLE_BASEBOARD_BROX
select DRIVERS_AUDIO_SOF
select DRIVERS_GFX_GENERIC
select HAVE_SLP_S0_GATE
- select MEMORY_SOLDERDOWN
+ select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_GREENBAYUPOC
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CRASHLOG
select SOC_INTEL_RAPTORLAKE
@@ -70,6 +70,7 @@ config BOARD_GOOGLE_LOTSO
config BOARD_GOOGLE_GREENBAYUPOC
select BOARD_GOOGLE_BASEBOARD_BROX
+ select MEMORY_SODIMM
if BOARD_GOOGLE_BROX_COMMON
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk
new file mode 100644
index 0000000000..be05cd4e5c
--- /dev/null
+++ b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory.c b/src/mainboard/google/brox/variants/greenbayupoc/memory.c
new file mode 100644
index 0000000000..3cfa79e950
--- /dev/null
+++ b/src/mainboard/google/brox/variants/greenbayupoc/memory.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+ .type = MEM_TYPE_DDR4,
+
+ .rcomp = {
+ .resistor = 100,
+ .targets = {50, 20, 25, 25, 25},
+ },
+
+ .LpDdrDqDqsReTraining = 1,
+
+ .ect = 1,
+
+ .UserBd = BOARD_TYPE_MOBILE,
+
+ .ddr_config = {
+ .dq_pins_interleaved = 0,
+ },
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+ return &ddr4_mem_config;
+}
+
+bool variant_is_half_populated(void)
+{
+ return false;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+ spd_info->topo = MEM_TOPO_DIMM_MODULE;
+ spd_info->smbus[0].addr_dimm[0] = 0x50;
+ spd_info->smbus[0].addr_dimm[1] = 0x51;
+ spd_info->smbus[1].addr_dimm[0] = 0x52;
+ spd_info->smbus[1].addr_dimm[1] = 0x53;
+}
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk
deleted file mode 100644
index eace2e443e..0000000000
--- a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-
-SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt
deleted file mode 100644
index 2e0f37a10a..0000000000
--- a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
-
-DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt
deleted file mode 100644
index 2499005682..0000000000
--- a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.mk and dram_id.generated.txt by running the
-# part_id_gen tool from util/spd_tools.
-# See util/spd_tools/README.md for more details and instructions.
-
-# Part Name
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
index ee65135d88..aeb4de594b 100644
--- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb
@@ -9,6 +9,7 @@ end
chip soc/intel/alderlake
device domain 0 on
+ device ref smbus on end
end
end