mb/google/auron: Refactor memory-down SPD handling

Variants only need to provide the SPD index and whether said index
corresponds to a dual-channel configuration, which can be achieved
without using `pei_data`. Add two functions that return the values
and use them in `spd.c` at mainboard level.

Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

7 files changed, 53 insertions, 89 deletions

diff --git a/src/mainboard/google/auron/spd.c b/src/mainboard/google/auron/spd.c
index 539026b332..52e4d63915 100644
--- a/src/mainboard/google/auron/spd.c
+++ b/src/mainboard/google/auron/spd.c
@@ -19,6 +19,8 @@
 #define SPD_PART_OFF		128
 #define SPD_PART_LEN		18
 
+#define SPD_LEN			256
+
 static void mainboard_print_spd_info(uint8_t spd[])
 {
 	const int spd_banks[8] = {  8, 16, 32, 64, -1, -1, -1, -1 };
@@ -69,7 +71,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
 	}
 }
 
-void fill_spd_for_index(uint8_t spd[], unsigned int spd_index)
+static void fill_spd_for_index(uint8_t spd[], unsigned int spd_index)
 {
 	size_t spd_file_len;
 	uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
@@ -95,3 +97,16 @@ void fill_spd_for_index(uint8_t spd[], unsigned int spd_index)
 
 	mainboard_print_spd_info(spd);
 }
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+	const unsigned int spd_index = variant_get_spd_index();
+
+	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
+
+	if (variant_is_dual_channel(spd_index))
+		memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
+	else
+		pei_data->dimm_channel1_disabled = 3;
+}
diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h
index ba4c58a9e1..d471576bc4 100644
--- a/src/mainboard/google/auron/variant.h
+++ b/src/mainboard/google/auron/variant.h
@@ -11,8 +11,7 @@ int variant_smbios_data(struct device *dev, int *handle,
 			unsigned long *current);
 void lan_init(void);
 
-void fill_spd_for_index(uint8_t spd[], unsigned int index);
-
-#define SPD_LEN			256
+unsigned int variant_get_spd_index(void);
+bool variant_is_dual_channel(const unsigned int spd_index);
 
 #endif
diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
index 5527a2e962..f2401d4be7 100644
--- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
+++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c
@@ -1,21 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <endian.h>
-#include <string.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron/ec.h>
 #include <mainboard/google/auron/variant.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* Auron board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
 #define SPD_GPIO_BIT1		9
 #define SPD_GPIO_BIT2		47
 
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {
 		SPD_GPIO_BIT0,
@@ -23,15 +16,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 		SPD_GPIO_BIT2,
 		-1,
 	};
+	return get_gpios(gpio_vector);
+}
 
-	const unsigned int spd_index = get_gpios(gpio_vector);
-
-	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* Index 0-2 are 4GB config with both CH0 and CH1.
 	 * Index 4-6 are 2GB config with CH0 only. */
-	if (spd_index > 3)
-		pei_data->dimm_channel1_disabled = 3;
-	else
-		memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
+	return !(spd_index > 3);
 }
diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
index 5527a2e962..f2401d4be7 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
+++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
@@ -1,21 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <endian.h>
-#include <string.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron/ec.h>
 #include <mainboard/google/auron/variant.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* Auron board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
 #define SPD_GPIO_BIT1		9
 #define SPD_GPIO_BIT2		47
 
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {
 		SPD_GPIO_BIT0,
@@ -23,15 +16,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 		SPD_GPIO_BIT2,
 		-1,
 	};
+	return get_gpios(gpio_vector);
+}
 
-	const unsigned int spd_index = get_gpios(gpio_vector);
-
-	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* Index 0-2 are 4GB config with both CH0 and CH1.
 	 * Index 4-6 are 2GB config with CH0 only. */
-	if (spd_index > 3)
-		pei_data->dimm_channel1_disabled = 3;
-	else
-		memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
+	return !(spd_index > 3);
 }
diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c
index 90958c8dd4..d144e20ec3 100644
--- a/src/mainboard/google/auron/variants/gandof/spd/spd.c
+++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c
@@ -1,21 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <endian.h>
-#include <string.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron/ec.h>
 #include <mainboard/google/auron/variant.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* Gandof board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
 #define SPD_GPIO_BIT1		9
 #define SPD_GPIO_BIT2		47
 
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {
 		SPD_GPIO_BIT0,
@@ -23,15 +16,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 		SPD_GPIO_BIT2,
 		-1,
 	};
+	return get_gpios(gpio_vector);
+}
 
-	const unsigned int spd_index = get_gpios(gpio_vector);
-
-	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* Index 0-2 are 4GB config with both CH0 and CH1.
 	 * Index 4-6 are 2GB config with CH0 only. */
-	if (spd_index > 3)
-		pei_data->dimm_channel1_disabled = 3;
-	else
-		memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
+	return !(spd_index > 3);
 }
diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c
index a54fe4a7fb..33e8c9b55d 100644
--- a/src/mainboard/google/auron/variants/lulu/spd/spd.c
+++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c
@@ -1,13 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <endian.h>
-#include <string.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron/ec.h>
 #include <mainboard/google/auron/variant.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* Lulu board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -15,8 +9,7 @@
 #define SPD_GPIO_BIT2		47
 #define SPD_GPIO_BIT3		8
 
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {
 		SPD_GPIO_BIT0,
@@ -25,17 +18,11 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 		SPD_GPIO_BIT3,
 		-1,
 	};
+	return get_gpios(gpio_vector);
+}
 
-	const unsigned int spd_index = get_gpios(gpio_vector);
-
-	/* CH0 */
-	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* CH1 not used in 2GB configurations */
-	if (!((spd_index == 0b0000) || (spd_index == 0b0011) ||
-	    (spd_index == 0b1010))) {
-		memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
-	} else {
-		pei_data->dimm_channel1_disabled = 3;
-	}
+	return !((spd_index == 0b0000) || (spd_index == 0b0011) || (spd_index == 0b1010));
 }
diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c
index 9b27db5187..f12744143b 100644
--- a/src/mainboard/google/auron/variants/samus/spd/spd.c
+++ b/src/mainboard/google/auron/variants/samus/spd/spd.c
@@ -1,13 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <endian.h>
-#include <string.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron/ec.h>
 #include <mainboard/google/auron/variant.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* Samus board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		69
@@ -15,8 +9,7 @@
 #define SPD_GPIO_BIT2		67
 #define SPD_GPIO_BIT3		65
 
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {
 		SPD_GPIO_BIT0,
@@ -25,11 +18,11 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 		SPD_GPIO_BIT3,
 		-1,
 	};
+	return get_gpios(gpio_vector);
+}
 
-	const unsigned int spd_index = get_gpios(gpio_vector);
-
-	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* Assume same memory in both channels */
-	memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
+	return true;
 }