diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-05-06 00:22:01 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-11 12:53:10 +0000 |
| commit | 0e0c2b345e6caa088e43e598dc483cc3624a0668 (patch) | |
| tree | 7454792ab1a52463b49d2f2beb57118039a17fc9 /src/mainboard/google | |
| parent | a83d8ab0f8da00c21bd2962857a5a24f97376d4e (diff) | |
mb/google/dedede/var/metaknight: Update LTE USB port configuration
Update LTE USB port configuration at run-time after probing the firmware
config. By default the concerned USB port takes the Type-A port
configuration.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight
Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Diffstat (limited to 'src/mainboard/google')
3 files changed, 58 insertions, 21 deletions
diff --git a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc index 67a7ab235a..2479ae9e66 100644 --- a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc +++ b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 0052ec72d3..c8c56f9a9f 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -69,23 +69,12 @@ chip soc/intel/jasperlake chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" - register "reset_off_delay_ms" = "10" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "enable_delay_ms" = "20" - device usb 2.3 on - probe DB_PORTS DB_PORTS_LTE_HDMI - end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Multi-use Port"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 2.3 on probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_LTE_HDMI end end chip drivers/usb/acpi @@ -99,18 +88,12 @@ chip soc/intel/jasperlake device usb 2.6 on end end chip drivers/usb/acpi - register "desc" = ""LTE"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on - probe DB_PORTS DB_PORTS_LTE_HDMI - end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Multi-use Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 3.3 on probe DB_PORTS DB_PORTS_1A_HDMI + probe DB_PORTS DB_PORTS_LTE_HDMI end end end diff --git a/src/mainboard/google/dedede/variants/metaknight/ramstage.c b/src/mainboard/google/dedede/variants/metaknight/ramstage.c new file mode 100644 index 0000000000..3c8e1967f6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/ramstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> + +#define LTE_USB_PORT_ID 3 +#define LTE_USB_PORT_TYPE 2 +static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17); +static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10); + +static void update_xhci_devtree(void) +{ + struct device *xhci, *hub = NULL, *port = NULL; + struct drivers_usb_acpi_config *config; + + xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!xhci) { + printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); + return; + } + + while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID) + continue; + + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI))) + continue; + + config = port->chip_info; + config->type = UPC_TYPE_INTERNAL; + if (port->path.usb.port_type == LTE_USB_PORT_TYPE) { + config->has_power_resource = 1; + memcpy(&config->reset_gpio, <e_reset_gpio, + sizeof(config->reset_gpio)); + config->reset_off_delay_ms = 10; + memcpy(&config->enable_gpio, <e_enable_gpio, + sizeof(config->enable_gpio)); + config->enable_delay_ms = 20; + } + } + } +} + +void variant_devtree_update(void) +{ + update_xhci_devtree(); +} |