diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-04 11:18:39 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-07 04:53:39 +0000 |
| commit | 0caf80d8aaa383d40618343f14ed78774108053d (patch) | |
| tree | 58dcb504e8ac9e4d6d6aff1ea7749b89c7fc432b /src/mainboard/google | |
| parent | d4e68eb4147c5306f50e027950142db9ba46609c (diff) | |
bd82x6x boards: Drop redundant `c2_latency`
If unspecified, chipset code already uses 101, and 0x65 == 101.
Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 7cdb8a30e9..9dee30f54d 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -60,8 +60,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 |