diff options
| author | Lin Huang <hl@rock-chips.com> | 2017-07-25 09:32:47 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-08-01 20:00:18 +0000 |
| commit | 05c3e846223326620ccf3b880fa97f630d34a7ed (patch) | |
| tree | 31cd2211dff0f3186e5a6673b3abda9854ab4a58 /src/mainboard/google | |
| parent | 6c581bc43ffd857d626b0918b580d6e14f2c5906 (diff) | |
google/gru: Use 1.8V powerdomain for gpio4cd on Scarlet
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/gru/bootblock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 7359f2a302..c5ab28a7b0 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -44,6 +44,10 @@ void bootblock_mainboard_early_init(void) */ write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0)); + /* Scarlet gpio4cd iodomain is 1.8V */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) + write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3)); + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { /* Enable rails powering GPIO blocks, among other things. These are EC-controlled on Scarlet and already on. */ |