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authorDtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>2022-06-23 15:02:11 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-06-27 13:46:00 +0000
commit035e31920aa34d5a730869c87ffeb10ccf0ab2db (patch)
treea36690edb296e1284053fe728be8614ce8113f75 /src/mainboard/google
parentb6c3a0325b9b0462cca81ea4134efb6b73756577 (diff)
mb/google/brya/var/kinox: Modify ddi_ports_config
Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf. DDI_PORT_A = DP DDI_PORT_B = HDMI DDI_PORT_1 = Type-C DP DDI_PORT_2 = DP or HDMI BUG=b:233338341 TEST=Boot to Chrome OS and check all display port working Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/variants/kinox/overridetree.cb7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb
index 913ff015f8..7649064c48 100644
--- a/src/mainboard/google/brya/variants/kinox/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb
@@ -56,6 +56,13 @@ chip soc/intel/alderlake
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}"
+ register "ddi_ports_config" = "{
+ [DDI_PORT_A] = DDI_ENABLE_HPD,
+ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_1] = DDI_ENABLE_HPD,
+ [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC
+ }"
+
device domain 0 on
device ref dtt on
chip drivers/intel/dptf