diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-05 12:34:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-07 11:34:11 +0000 |
| commit | 023968453e13f09420c8d6ecdeeb42a229c0ff09 (patch) | |
| tree | 072bece04599c898875992aae35e8d4b6005a7e7 /src/mainboard/google | |
| parent | d047927168e63004d0b4fa521b48d321af1b0ac6 (diff) | |
sb/intel/bd82x6x: Use array for PCIe ASPM overrides
Using an array reduces the amount of boilerplate code.
Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9dee30f54d..725cbd1700 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -72,7 +72,7 @@ chip northbridge/intel/sandybridge device pci 1c.1 on end # PCIe Port #2 (ETH0) device pci 1c.2 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1ec596eda1..914ab601e0 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -76,7 +76,7 @@ chip northbridge/intel/sandybridge device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (WLAN) device pci 1c.2 on end # PCIe Port #3 (Card Reader) - register "pcie_aspm_f2" = "0x3" + register "pcie_aspm[2]" = "0x3" device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 on end # PCIe Port #6 (LAN) |