diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-12-16 10:13:35 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-06 17:33:16 +0000 |
| commit | ead253a366cbad63d00ffdc914ff9f7f6f534e42 (patch) | |
| tree | 9b961f4fc060319eae411ef651f16113c45e6f90 /src/mainboard/google | |
| parent | 4e80fae2367d3a0a64ac2896dc654e0cf842fc4e (diff) | |
mb/google/zork/mainboard: Remove unused pirq_data
This table was wrong. It's also produced by the SoC code now.
BUG=b:170595019
TEST=Verify PCI IRQ: log messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/zork/mainboard.c | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 824a87dab4..94a64bd078 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -51,30 +51,6 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), "PIC and APIC FCH interrupt tables must be the same size"); /* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - -/* * This controls the device -> IRQ routing. * * Hardcoded IRQs: @@ -133,9 +109,6 @@ static void init_tables(void) static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } |