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authorJohn Zhao <john.zhao@intel.com>2020-07-27 13:22:11 -0700
committerNick Vaccaro <nvaccaro@google.com>2020-07-29 22:46:29 +0000
commitbd615d6f9379cc454c728c8f79f13612f3fb7a19 (patch)
tree57bd7c98bc93aaf70576f75d336b4026098c870c /src/mainboard/google
parent048d9b5cba64d1dbffc40ee19a5263aeac628e3c (diff)
soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
Update configuration for both of TCSS D3Hot and D3Cold. It is expected D3Hot is enabled for all platforms. Because there are known limitations for D3Cold enabling on pre-QS platform, this change reads cpu id and disables D3Cold for pre-QS platform. For QS platform, D3Cold is configured to be enabled. BUG=None TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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