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authorShreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>2020-12-03 15:06:20 -0800
committerFurquan Shaikh <furquan@google.com>2020-12-14 23:05:57 +0000
commit860c68449da9a6752fedb752cacdf0ac8bd6a61d (patch)
tree2e40902fac32921e6e20c24d31e4bc60ded8ce0a /src/mainboard/google
parent87c7ec7c0677ec5fda4a9cebb95c06edb23a96ba (diff)
src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config option. Select CAR_HAS_SF_MASKS for Tigerlake. During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x are not being reset to default as per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5. Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient. Bug=b:171601324 BRANCH=volteer Test=Build and boot to ChromeOS on Delbin. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
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