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authorWayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>2021-02-02 18:20:03 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-02-03 20:11:40 +0000
commit585f4d46cca95d8b8219d21e0af5fb487827318a (patch)
tree97c0bbb07e86c6271709ad4ad4751f316a33a8bb /src/mainboard/google
parented6bda2818a8ce79a36f9e5a2e30f1be6299724a (diff)
mb/google/volteer/variants/drobit: Configure USB2 port for Type-CHEADmaster
USB2 ports assigned to type-C connector need to be configured properly by the USB2_PORT_TYPE_C. and also modify the description of USB port. BUG=b:177480902 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the typeC port function is normal by manual. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/volteer/variants/drobit/overridetree.cb11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
index 17143b84a6..608535e834 100644
--- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb
@@ -21,6 +21,9 @@ chip soc/intel/tigerlake
.tdp_pl4 = 105,
}"
+ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1
+ register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # Type-C port 0
+
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
@@ -178,7 +181,7 @@ chip soc/intel/tigerlake
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Port C1 (DB)""
+ register "desc" = ""USB3 Type-C Port C1 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref tcss_usb3_port2 on
@@ -192,13 +195,13 @@ chip soc/intel/tigerlake
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A Port A0 (MLB)""
+ register "desc" = ""USB2 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB2 Type-C Port C1 (DB)""
+ register "desc" = ""USB2 Type-C Port C1 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port4 on
@@ -223,7 +226,7 @@ chip soc/intel/tigerlake
device ref usb2_port10 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Port A0 (MLB)""
+ register "desc" = ""USB3 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb3_port1 on end