diff options
| author | Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> | 2021-02-04 13:16:24 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:23:22 +0000 |
| commit | 3c6ad8d1843d63c37c8f413263fd140fa78f866a (patch) | |
| tree | f35d730c51677399d1e057924c7a92e742710501 /src/mainboard/google | |
| parent | fbad99f347957871269d197b80df18e2912c622f (diff) | |
mb/google/volteer: Enable external bypass, clkgate & phygate
This change sets the soc config options for external_bypass,
external_clk_gate and external_phy_gate.
BUG=b:177821896
TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ccde132176..6a826c0bd2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -255,6 +255,15 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" + # Enable External Bypass + register "external_bypass" = "1" + + # Enable External Clk Gate + register "external_clk_gated" = "1" + + # Enable External Phy Gate + register "external_phy_gated" = "1" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 38, |