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authorKenji Chen <kenji.chen@intel.com>2014-10-04 01:14:44 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-03-23 13:11:15 +0100
commit31c6e632cf607ad8364c49b934f726ef02486d46 (patch)
treedc4a40bf1f4358719837141d4a9044304fcf03d9 /src/mainboard/google
parent431e51ec2aeb739504bbb09c342091d407fa8ca1 (diff)
PCIe: Add L1 Sub-State support.
Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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