diff options
| author | Seunghwan Kim <sh_.kim@samsung.com> | 2019-12-09 11:12:08 +0900 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-10 11:17:29 +0000 |
| commit | 0a2de7b538e3d6490a8d748bc8b8b9b7511c81bc (patch) | |
| tree | 1749306558d42f580707ebb4be1846fe1187a423 /src/mainboard/google | |
| parent | 13746076e95a611b56dfe37519685ae125172bb4 (diff) | |
mb/google/kohaku: Update TCC offset setting
This change sets TCC offset to 10 for kohaku.
BUG=b:144532818
BRANCH=firmware-hatch-12672.B
TEST=Checked thermal and performance efficiency internally (b:144532818)
Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Grace Kao <grace.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index d515ecc44d..cd5ce0e816 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -2,8 +2,6 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "8" register "tdp_pl2_override" = "51" - register "tcc_offset" = "35" # TCC of 65C - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, |