diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-05-26 12:01:19 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-27 19:55:30 +0200 |
| commit | 07dd474d658545b6b284195e7a003c6fe8ca8c44 (patch) | |
| tree | b15a453526883d9b97091ae850d38f216b72be3b /src/mainboard/google | |
| parent | 2b56ba5a4f90322a42802957aab3492db049a202 (diff) | |
mainboard/google/reef: increase BIOS region size
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.
Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/reef/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/reef/chromeos.fmd | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index e49e8b6b75..5d8ded68f6 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -19,7 +19,7 @@ config BOOT_MEDIA_SPI_BUS config IFD_BIOS_END hex - default 0x6FF000 + default 0x77F000 config IFD_BIOS_START hex diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index a3fb8b52b1..3f7c3aaf34 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -10,9 +10,9 @@ FLASH 8M { RO_FRID@0x4800 0x40 RO_FRID_PAD@0x4840 0x7c0 COREBOOT(CBFS)@0x5000 0x17b000 + GBB@0x180000 0x40000 # logical boot partition 2. Remove with updated CSE - SIGN_CSE@0x180000 0x10000 - GBB@0x190000 0x70000 + SIGN_CSE@0x1c0000 0x10000 } } MISC_RW@0x400000 0x1a000 { @@ -34,6 +34,6 @@ FLASH 8M { FW_MAIN_B(CBFS)@0x10000 0x162fc0 RW_FWID_B@0x172fc0 0x40 } - DEVICE_EXTENSION@0x700000 0x100000 + DEVICE_EXTENSION@0x77f000 0x80000 } |