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authorGaggery Tsai <gaggery.tsai@intel.com>2018-02-07 17:17:05 +0800
committerMartin Roth <martinroth@google.com>2018-02-20 23:18:50 +0000
commitcb304c1d85ff0a289c8a7244bf6e8adac07cd624 (patch)
treeabd41d6821f0ec7d74cf251aff097072f05988e4 /src/mainboard/google
parent9b3da9fc57c8b5739db365e193e214dd3bf758bc (diff)
mb/google/poopy/variants/nami: Add Pmax setting
This patch adds the Pmax setting in device tree. The Pmax is from MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W. BUG=b:72138778 BRANCH=None TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index c4819663cc..b830912562 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -229,6 +229,7 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
register "tcc_offset" = "10" # TCC of 90C
+ register "psys_pmax" = "101"
# Lock Down
register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"