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authorCaveh Jalali <caveh@chromium.org>2019-02-01 20:21:26 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-22 11:10:53 +0000
commitab770083952dbe39987650a9570967b1436ce785 (patch)
treefc7cf71651694f0ba14f736e43a974464776edd9 /src/mainboard/google
parentd6f71d03f1f588e02c5792c7ca3be8d12127b603 (diff)
mb/google/poppy/variants/atlas: move WiFi wake to GPP_B7
The latest rev. of the atlas board moves the WiFi wake source from WAKE# to GPP_B7. The original GPP_A0 in the device tree is just wrong. This also reconfigures DW1 to the GPP_B group so we can use GPP_B7 as a wake source. GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't actually enable WiFi wake. We'll follow up with another patch to set up GPP_B7 properly on boards that support it. BUG=b:122327852 BRANCH=none TEST=atlas still boots Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index adf51b7877..5b49884801 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -12,7 +12,7 @@ chip soc/intel/skylake
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_A"
- register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw1" = "GPP_B"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
@@ -345,7 +345,7 @@ chip soc/intel/skylake
end # I2C #4 - Audio
device pci 1c.0 on
chip drivers/intel/wifi
- register "wake" = "GPE0_DW0_00"
+ register "wake" = "GPE0_DW1_07" # GPP_B7
device pci 00.0 on end
end
end # PCI Express Port 1