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authorDuncan Laurie <dlaurie@chromium.org>2016-12-19 19:50:10 -0800
committerDuncan Laurie <dlaurie@chromium.org>2016-12-20 17:12:33 +0100
commita4464140f9467f76f1ee515b90451d4723b51ca1 (patch)
treeba98b3e2d2b8d17690a73214dbf7d4d6db55bdb6 /src/mainboard/google
parentf171e6645df0ed9bc214b408eca7e8fdc7c04075 (diff)
google/eve: Fix configuration of some GPIOs
GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/eve/gpio.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index 34ae3a45b6..10642e98cf 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = {
/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
-/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
-/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
-/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
-/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* TOUCHPAD_SPI */
+/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */
+/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */
+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
@@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = {
/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */
-/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
+/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),